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| author | Shlomo Hecht <shlomo@twine-s.com> | 2018-03-06 12:09:02 +0200 |
|---|---|---|
| committer | Shlomo Hecht <shlomo@twine-s.com> | 2018-03-06 12:09:02 +0200 |
| commit | fb2d080fbbcea3a91e598b4ea8837a230de6a319 (patch) | |
| tree | 6b3ce09a252d2ebab8189a92b3326ffbba6dbe4b /Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config | |
| parent | d734bb5cf08ba2433b74fc86a8858d2437d1a237 (diff) | |
| download | Tango-fb2d080fbbcea3a91e598b4ea8837a230de6a319.tar.gz Tango-fb2d080fbbcea3a91e598b4ea8837a230de6a319.zip | |
A new forlder for embedded software in our common structure
Diffstat (limited to 'Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config')
6 files changed, 1799 insertions, 0 deletions
diff --git a/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/MCU_MAIN_pinout.c b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/MCU_MAIN_pinout.c new file mode 100644 index 000000000..2899a6a41 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/MCU_MAIN_pinout.c @@ -0,0 +1,996 @@ +//***************************************************************************** +// +// Configure the device pins for different signals +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +// This file was automatically generated on 25.2.2018 at 10:21:42 +// by TI PinMux version 4.0.1510 +// +//***************************************************************************** + +#include <stdbool.h> +#include <stdint.h> +#include "inc/hw_gpio.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/gpio.h" +#include "driverlib/pin_map.h" +#include "driverlib/rom.h" +#include "driverlib/rom_map.h" +#include "driverlib/sysctl.h" +#include "pinout.h" + +//***************************************************************************** +// +//! \addtogroup pinout_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Configures the device pins for the customer specific usage. +//! +//! \return None. +// +//***************************************************************************** +void +PinoutSet(void) +{ + // + // Enable Peripheral Clocks + // + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT); + + // + // Configure the GPIO Pin Mux for PD1 + // for AIN14 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PE3 + // for AIN0 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PK1 + // for AIN17 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PE6 + // for AIN20 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_6); + + // + // Unlock the Port Pin and Set the Commit Bit + // + HWREG(GPIO_PORTD_BASE+GPIO_O_LOCK) = GPIO_LOCK_KEY; + HWREG(GPIO_PORTD_BASE+GPIO_O_CR) |= GPIO_PIN_7; + HWREG(GPIO_PORTD_BASE+GPIO_O_LOCK) = 0x0; + + // + // Configure the GPIO Pin Mux for PD7 + // for AIN4 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PD5 + // for AIN6 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PD0 + // for AIN15 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PD3 + // for AIN12 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PE1 + // for AIN2 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PB5 + // for AIN11 + // + MAP_GPIOPinTypeADC(GPIO_PORTB_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PK3 + // for AIN19 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PK0 + // for AIN16 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PD2 + // for AIN13 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PE4 + // for AIN9 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_4); + + // + // Unlock the Port Pin and Set the Commit Bit + // + HWREG(GPIO_PORTE_BASE+GPIO_O_LOCK) = GPIO_LOCK_KEY; + HWREG(GPIO_PORTE_BASE+GPIO_O_CR) |= GPIO_PIN_7; + HWREG(GPIO_PORTE_BASE+GPIO_O_LOCK) = 0x0; + + // + // Configure the GPIO Pin Mux for PE7 + // for AIN21 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PE5 + // for AIN8 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PE2 + // for AIN1 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PE0 + // for AIN3 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PK2 + // for AIN18 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PB4 + // for AIN10 + // + MAP_GPIOPinTypeADC(GPIO_PORTB_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PD4 + // for AIN7 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PD6 + // for AIN5 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PT2 + // for CAN1RX + // + MAP_GPIOPinConfigure(GPIO_PT2_CAN1RX); + MAP_GPIOPinTypeCAN(GPIO_PORTT_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PT3 + // for CAN1TX + // + MAP_GPIOPinConfigure(GPIO_PT3_CAN1TX); + MAP_GPIOPinTypeCAN(GPIO_PORTT_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PK4 + // for EPI0S32 + // + MAP_GPIOPinConfigure(GPIO_PK4_EPI0S32); + GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PL4 + // for EPI0S26 + // + MAP_GPIOPinConfigure(GPIO_PL4_EPI0S26); + GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PK6 + // for EPI0S25 + // + MAP_GPIOPinConfigure(GPIO_PK6_EPI0S25); + GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PL0 + // for EPI0S16 + // + MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16); + GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PG0 + // for EPI0S11 + // + MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11); + GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PA6 + // for EPI0S8 + // + MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8); + GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PH1 + // for EPI0S1 + // + MAP_GPIOPinConfigure(GPIO_PH1_EPI0S1); + GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PN3 + // for EPI0S30 + // + MAP_GPIOPinConfigure(GPIO_PN3_EPI0S30); + GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PB2 + // for EPI0S27 + // + MAP_GPIOPinConfigure(GPIO_PB2_EPI0S27); + GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PN4 + // for EPI0S34 + // + MAP_GPIOPinConfigure(GPIO_PN4_EPI0S34); + GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PQ1 + // for EPI0S21 + // + MAP_GPIOPinConfigure(GPIO_PQ1_EPI0S21); + GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PL3 + // for EPI0S19 + // + MAP_GPIOPinConfigure(GPIO_PL3_EPI0S19); + GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PM0 + // for EPI0S15 + // + MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15); + GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PM2 + // for EPI0S13 + // + MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13); + GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PB3 + // for EPI0S28 + // + MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28); + GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PQ3 + // for EPI0S23 + // + MAP_GPIOPinConfigure(GPIO_PQ3_EPI0S23); + GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PG1 + // for EPI0S10 + // + MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10); + GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PK5 + // for EPI0S31 + // + MAP_GPIOPinConfigure(GPIO_PK5_EPI0S31); + GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PN2 + // for EPI0S29 + // + MAP_GPIOPinConfigure(GPIO_PN2_EPI0S29); + GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PH3 + // for EPI0S3 + // + MAP_GPIOPinConfigure(GPIO_PH3_EPI0S3); + GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PC5 + // for EPI0S6 + // + MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6); + GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PA7 + // for EPI0S9 + // + MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9); + GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PH0 + // for EPI0S0 + // + MAP_GPIOPinConfigure(GPIO_PH0_EPI0S0); + GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PC4 + // for EPI0S7 + // + MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7); + GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PL1 + // for EPI0S17 + // + MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17); + GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PL5 + // for EPI0S33 + // + MAP_GPIOPinConfigure(GPIO_PL5_EPI0S33); + GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PN5 + // for EPI0S35 + // + MAP_GPIOPinConfigure(GPIO_PN5_EPI0S35); + GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PM1 + // for EPI0S14 + // + MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14); + GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PK7 + // for EPI0S24 + // + MAP_GPIOPinConfigure(GPIO_PK7_EPI0S24); + GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PC7 + // for EPI0S4 + // + MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4); + GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PL2 + // for EPI0S18 + // + MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18); + GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PM3 + // for EPI0S12 + // + MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12); + GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PQ0 + // for EPI0S20 + // + MAP_GPIOPinConfigure(GPIO_PQ0_EPI0S20); + GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PQ2 + // for EPI0S22 + // + MAP_GPIOPinConfigure(GPIO_PQ2_EPI0S22); + GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PC6 + // for EPI0S5 + // + MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5); + GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PH2 + // for EPI0S2 + // + MAP_GPIOPinConfigure(GPIO_PH2_EPI0S2); + GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PB6 + // for GPIO_PB6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PB7 + // for GPIO_PB7 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PJ3 + // for GPIO_PJ3 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PQ6 + // for GPIO_PQ6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTQ_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PS5 + // for GPIO_PS5 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTS_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PS7 + // for GPIO_PS7 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTS_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PN7 + // for GPIO_PN7 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTN_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PS6 + // for GPIO_PS6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTS_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PT1 + // for GPIO_PT1 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTT_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PT0 + // for GPIO_PT0 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTT_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PS4 + // for GPIO_PS4 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTS_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PN6 + // for GPIO_PN6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PF6 + // for GPIO_PF6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PM7 + // for GPIO_PM7 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PM6 + // for GPIO_PM6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PF7 + // for GPIO_PF7 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTF_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PR3 + // for GPIO_PR3 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTR_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PM4 + // for GPIO_PM4 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PJ2 + // for GPIO_PJ2 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PM5 + // for GPIO_PM5 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PH4 + // for GPIO_PH4 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PH7 + // for GPIO_PH7 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PH6 + // for GPIO_PH6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PH5 + // for GPIO_PH5 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PQ7 + // for GPIO_PQ7 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PJ4 + // for GPIO_PJ4 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PJ5 + // for GPIO_PJ5 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PS2 + // for GPIO_PS2 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTS_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PS3 + // for GPIO_PS3 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTS_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PJ7 + // for GPIO_PJ7 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PS1 + // for GPIO_PS1 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTS_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PP5 + // for GPIO_PP5 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PP3 + // for GPIO_PP3 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PS0 + // for GPIO_PS0 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTS_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PN1 + // for GPIO_PN1 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PN0 + // for GPIO_PN0 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PJ0 + // for GPIO_PJ0 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PP4 + // for GPIO_PP4 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PJ1 + // for GPIO_PJ1 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PP0 + // for GPIO_PP0 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PP1 + // for GPIO_PP1 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PP2 + // for GPIO_PP2 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PR2 + // for GPIO_PR2 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTR_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PJ6 + // for GPIO_PJ6 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PP6 + // for GPIO_PP6 + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PP7 + // for GPIO_PP7 + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PR6 + // for I2C4SCL + // + MAP_GPIOPinConfigure(GPIO_PR6_I2C4SCL); + MAP_GPIOPinTypeI2CSCL(GPIO_PORTR_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PR7 + // for I2C4SDA + // + MAP_GPIOPinConfigure(GPIO_PR7_I2C4SDA); + MAP_GPIOPinTypeI2C(GPIO_PORTR_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PR4 + // for I2C3SCL + // + MAP_GPIOPinConfigure(GPIO_PR4_I2C3SCL); + MAP_GPIOPinTypeI2CSCL(GPIO_PORTR_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PR5 + // for I2C3SDA + // + MAP_GPIOPinConfigure(GPIO_PR5_I2C3SDA); + MAP_GPIOPinTypeI2C(GPIO_PORTR_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PG2 + // for I2C2SCL + // + MAP_GPIOPinConfigure(GPIO_PG2_I2C2SCL); + MAP_GPIOPinTypeI2CSCL(GPIO_PORTG_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PG3 + // for I2C2SDA + // + MAP_GPIOPinConfigure(GPIO_PG3_I2C2SDA); + MAP_GPIOPinTypeI2C(GPIO_PORTG_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PR0 + // for I2C1SCL + // + MAP_GPIOPinConfigure(GPIO_PR0_I2C1SCL); + MAP_GPIOPinTypeI2CSCL(GPIO_PORTR_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PR1 + // for I2C1SDA + // + MAP_GPIOPinConfigure(GPIO_PR1_I2C1SDA); + MAP_GPIOPinTypeI2C(GPIO_PORTR_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PF1 + // for SSI3XDAT0 + // + MAP_GPIOPinConfigure(GPIO_PF1_SSI3XDAT0); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PF5 + // for SSI3XDAT3 + // + MAP_GPIOPinConfigure(GPIO_PF5_SSI3XDAT3); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PF0 + // for SSI3XDAT1 + // + MAP_GPIOPinConfigure(GPIO_PF0_SSI3XDAT1); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PF2 + // for SSI3FSS + // + MAP_GPIOPinConfigure(GPIO_PF2_SSI3FSS); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PF4 + // for SSI3XDAT2 + // + MAP_GPIOPinConfigure(GPIO_PF4_SSI3XDAT2); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PF3 + // for SSI3CLK + // + MAP_GPIOPinConfigure(GPIO_PF3_SSI3CLK); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PG5 + // for SSI2XDAT0 + // + MAP_GPIOPinConfigure(GPIO_PG5_SSI2XDAT0); + MAP_GPIOPinTypeSSI(GPIO_PORTG_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PG4 + // for SSI2XDAT1 + // + MAP_GPIOPinConfigure(GPIO_PG4_SSI2XDAT1); + MAP_GPIOPinTypeSSI(GPIO_PORTG_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PG6 + // for SSI2FSS + // + MAP_GPIOPinConfigure(GPIO_PG6_SSI2FSS); + MAP_GPIOPinTypeSSI(GPIO_PORTG_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PG7 + // for SSI2CLK + // + MAP_GPIOPinConfigure(GPIO_PG7_SSI2CLK); + MAP_GPIOPinTypeSSI(GPIO_PORTG_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PA0 + // for U0RX + // + MAP_GPIOPinConfigure(GPIO_PA0_U0RX); + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PA1 + // for U0TX + // + MAP_GPIOPinConfigure(GPIO_PA1_U0TX); + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_1); + + // + // Configure the GPIO Pin Mux for PQ4 + // for U1RX + // + MAP_GPIOPinConfigure(GPIO_PQ4_U1RX); + MAP_GPIOPinTypeUART(GPIO_PORTQ_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PQ5 + // for U1TX + // + MAP_GPIOPinConfigure(GPIO_PQ5_U1TX); + MAP_GPIOPinTypeUART(GPIO_PORTQ_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PA4 + // for U3RX + // + MAP_GPIOPinConfigure(GPIO_PA4_U3RX); + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_4); + + // + // Configure the GPIO Pin Mux for PA5 + // for U3TX + // + MAP_GPIOPinConfigure(GPIO_PA5_U3TX); + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_5); + + // + // Configure the GPIO Pin Mux for PA2 + // for U4RX + // + MAP_GPIOPinConfigure(GPIO_PA2_U4RX); + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_2); + + // + // Configure the GPIO Pin Mux for PA3 + // for U4TX + // + MAP_GPIOPinConfigure(GPIO_PA3_U4TX); + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_3); + + // + // Configure the GPIO Pin Mux for PL6 + // for USB0DP + // + MAP_GPIOPinTypeUSBAnalog(GPIO_PORTL_BASE, GPIO_PIN_6); + + // + // Configure the GPIO Pin Mux for PL7 + // for USB0DM + // + MAP_GPIOPinTypeUSBAnalog(GPIO_PORTL_BASE, GPIO_PIN_7); + + // + // Configure the GPIO Pin Mux for PB0 + // for USB0ID + // + MAP_GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0); + + // + // Configure the GPIO Pin Mux for PB1 + // for USB0VBUS + // + MAP_GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_1); + +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/MCU_MAIN_pinout.h b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/MCU_MAIN_pinout.h new file mode 100644 index 000000000..ebbe0b7d6 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/MCU_MAIN_pinout.h @@ -0,0 +1,74 @@ +//***************************************************************************** +// pinout.h +// +// configure the device pins for different signals +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +// This file was automatically generated on 25.2.2018 at 10:21:42 +// by TI PinMux version 4.0.1510 +// +//***************************************************************************** + +#ifndef __DRIVERS_PINOUT_H__ +#define __DRIVERS_PINOUT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void PinoutSet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERS_PINOUT_H__ diff --git a/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin.c b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin.c new file mode 100644 index 000000000..1cb86ce4f --- /dev/null +++ b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin.c @@ -0,0 +1,621 @@ +//***************************************************************************** +// Copyright (c) 2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This file was automatically generated by the Tiva C Series PinMux Utility +// Version: 1.0.4 +// +//***************************************************************************** + +#include <stdint.h> +#include <stdbool.h> + +#include <inc/hw_types.h> +#include <inc/hw_memmap.h> +#include <inc/hw_gpio.h> +#include <driverlib/sysctl.h> +#include <driverlib/pin_map.h> +#include <driverlib/rom_map.h> +#include <driverlib/gpio.h> + +#include "Common/Sys_PinOut_Config/Pin.h" + +#ifdef ROM_GPIOPinTypeEthernetLED +#define MAP_GPIOPinTypeEthernetLED \ + ROM_GPIOPinTypeEthernetLED +#else +#define MAP_GPIOPinTypeEthernetLED \ + GPIOPinTypeEthernetLED +#endif + +//***************************************************************************** +void +PortFunctionInit(void) +{ + // + // Enable Peripheral Clocks + // + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C4); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART7); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART5); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM0); + + //hardware timers enabled manually because the pinout tool + //initialize automatically gpio per timer , deleting the gpio disables the timer + //manual initialization works well without gpios + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER3); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER4); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER5); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER6); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER7); + + + + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT); + MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0); + // + // Enable pin PD2 for ADC AIN13 + // + //MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2); + + // + // Enable pin PE3 for ADC AIN0 + // + //MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3); + + // + // Enable pin PK0 for ADC AIN16 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_0); + + // + // Enable pin PE6 for ADC AIN20 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_6); + + // + // Enable pin PD3 for ADC AIN12 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_3); + + // + // Enable pin PE1 for ADC AIN2 + // + //MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_1); + + // + // Enable pin PK1 for ADC AIN17 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_1); + + // + // Enable pin PK3 for ADC AIN19 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_3); + + // + // Enable pin PP6 for ADC AIN23 + // + MAP_GPIOPinTypeADC(GPIO_PORTP_BASE, GPIO_PIN_6); + + // + // Enable pin PE7 for ADC AIN21 + // First open the lock and select the bits we want to modify in the GPIO commit register. + // + HWREG(GPIO_PORTE_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY; + HWREG(GPIO_PORTE_BASE + GPIO_O_CR) = 0x80; + + // + // Now modify the configuration of the pins that we unlocked. + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_7); + + // + // Enable pin PB4 for ADC AIN10 + // + MAP_GPIOPinTypeADC(GPIO_PORTB_BASE, GPIO_PIN_4); + + // + // Enable pin PD6 for ADC AIN5 + // + MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_6); + + // + // Enable pin PE2 for ADC AIN1 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2); + + // + // Enable pin PE0 for ADC AIN3 + // + MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_0); + + // + // Enable pin PK2 for ADC AIN18 + // + MAP_GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_2); + + // + // Enable pin PP7 for ADC AIN22 + // + MAP_GPIOPinTypeADC(GPIO_PORTP_BASE, GPIO_PIN_7); + + // + // Enable pin PK4 for EPHY0 EN0LED0 + // + MAP_GPIOPinConfigure(GPIO_PK4_EN0LED0); + MAP_GPIOPinTypeEthernetLED(GPIO_PORTK_BASE, GPIO_PIN_4); + + // + // Enable pin PK5 for EPHY0 EN0LED2 + // + MAP_GPIOPinConfigure(GPIO_PK5_EN0LED2); + MAP_GPIOPinTypeEthernetLED(GPIO_PORTK_BASE, GPIO_PIN_5); + + // + // Enable pin PK6 for EPHY0 EN0LED1 + // + MAP_GPIOPinConfigure(GPIO_PK6_EN0LED1); + MAP_GPIOPinTypeEthernetLED(GPIO_PORTK_BASE, GPIO_PIN_6); + + // + // Enable pin PD0 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_0); + + // + // Enable pin PD1 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_1); + + // + // Enable pin PE4 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_4); + + // + // Enable pin PF7 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_7); + + // + // Enable pin PF6 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_6); + + // + // Enable pin PG4 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, GPIO_PIN_4); + + // + // Enable pin PG5 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, GPIO_PIN_5); + + // + // Enable pin PG0 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTG_BASE, GPIO_PIN_0); + + // + // Enable pin PG1 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTG_BASE, GPIO_PIN_1); + + // + // Enable pin PH2 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_2); + + // + // Enable pin PH0 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_0); + + // + // Enable pin PH4 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_4); + + // + // Enable pin PH6 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTH_BASE, GPIO_PIN_6); + + // + // Enable pin PH7 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTH_BASE, GPIO_PIN_7); + + // + // Enable pin PH5 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTH_BASE, GPIO_PIN_5); + + // + // Enable pin PH1 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_1); + + // + // Enable pin PH3 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_3); + + // + // Enable pin PJ7 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_7); + + // + // Enable pin PJ6 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_6); + + // + // Enable pin PJ2 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_2); + + // + // Enable pin PJ3 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_3); + + // + // Enable pin PL3 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_3); + + // + // Enable pin PL0 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_0); + + // + // Enable pin PL1 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_1); + + // + // Enable pin PL4 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_4); + + // + // Enable pin PL2 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_2); + + // + // Enable pin PL5 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_5); + + // + // Enable pin PM1 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_1); + + // + // Enable pin PM0 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_0); + + // + // Enable pin PM3 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_3); + + // + // Enable pin PM5 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_5); + + // + // Enable pin PM2 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_2); + + // + // Enable pin PN7 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTN_BASE, GPIO_PIN_7); + + // + // Enable pin PN1 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_1); + + // + // Enable pin PN4 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_4); + + // + // Enable pin PN0 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTN_BASE, GPIO_PIN_0); + + // + // Enable pin PP2 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_2); + + // + // Enable pin PP4 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_4); + + // + // Enable pin PP3 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_3); + + // + // Enable pin PP5 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_5); + + // + // Enable pin PP0 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTP_BASE, GPIO_PIN_0); + + // + // Enable pin PQ5 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_5); + + // + // Enable pin PQ7 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_7); + + // + // Enable pin PR3 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTR_BASE, GPIO_PIN_3); + + // + // Enable pin PR1 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTR_BASE, GPIO_PIN_1); + + // + // Enable pin PS4 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTS_BASE, GPIO_PIN_4); + + // + // Enable pin PS0 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTS_BASE, GPIO_PIN_0); + + // + // Enable pin PS2 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTS_BASE, GPIO_PIN_2); + + // + // Enable pin PS5 for GPIOOutput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTS_BASE, GPIO_PIN_5); + + // + // Enable pin PS3 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTS_BASE, GPIO_PIN_3); + + // + // Enable pin PT2 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTT_BASE, GPIO_PIN_2); + + // + // Enable pin PT0 for GPIOInput + // + MAP_GPIOPinTypeGPIOInput(GPIO_PORTT_BASE, GPIO_PIN_0); + + // + // Enable pin PA7 for GPIOInput + // + MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_7); + + // + // Enable pin PB3 for I2C0 I2C0SDA + // + MAP_GPIOPinConfigure(GPIO_PB3_I2C0SDA); + MAP_GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_3); + + // + // Enable pin PB2 for I2C0 I2C0SCL + // + MAP_GPIOPinConfigure(GPIO_PB2_I2C0SCL); + MAP_GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_2); + + // + // Enable pin PG6 for I2C4 I2C4SCL + // + MAP_GPIOPinConfigure(GPIO_PG6_I2C4SCL); + MAP_GPIOPinTypeI2CSCL(GPIO_PORTG_BASE, GPIO_PIN_6); + + // + // Enable pin PG7 for I2C4 I2C4SDA + // + MAP_GPIOPinConfigure(GPIO_PG7_I2C4SDA); + MAP_GPIOPinTypeI2C(GPIO_PORTG_BASE, GPIO_PIN_7); + + // + // Enable pin PR2 for PWM0 M0PWM2 + // + MAP_GPIOPinConfigure(GPIO_PR2_M0PWM2); + MAP_GPIOPinTypePWM(GPIO_PORTR_BASE, GPIO_PIN_2); + + // + // Enable pin PR7 for PWM0 M0PWM7 + // + MAP_GPIOPinConfigure(GPIO_PR7_M0PWM7); + MAP_GPIOPinTypePWM(GPIO_PORTR_BASE, GPIO_PIN_7); + + // + // Enable pin PR5 for PWM0 M0PWM5 + // + MAP_GPIOPinConfigure(GPIO_PR5_M0PWM5); + MAP_GPIOPinTypePWM(GPIO_PORTR_BASE, GPIO_PIN_5); + + // + // Enable pin PR0 for PWM0 M0PWM0 + // + MAP_GPIOPinConfigure(GPIO_PR0_M0PWM0); + MAP_GPIOPinTypePWM(GPIO_PORTR_BASE, GPIO_PIN_0); + + // + // Enable pin PA3 for SSI0 SSI0FSS + // + MAP_GPIOPinConfigure(GPIO_PA3_SSI0FSS); + MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + + // + // Enable pin PA4 for SSI0 SSI0XDAT0 + // + MAP_GPIOPinConfigure(GPIO_PA4_SSI0XDAT0); + MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_4); + + // + // Enable pin PA5 for SSI0 SSI0XDAT1 + // + MAP_GPIOPinConfigure(GPIO_PA5_SSI0XDAT1); + MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5); + + // + // Enable pin PA2 for SSI0 SSI0CLK + // + MAP_GPIOPinConfigure(GPIO_PA2_SSI0CLK); + MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2); + + // + // Enable pin PQ0 for SSI3 SSI3CLK + // + MAP_GPIOPinConfigure(GPIO_PQ0_SSI3CLK); + MAP_GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_0); + + // + // Enable pin PF1 for SSI3 SSI3XDAT0 + // + MAP_GPIOPinConfigure(GPIO_PF1_SSI3XDAT0); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_1); + + // + // Enable pin PQ1 for SSI3 SSI3FSS + // + MAP_GPIOPinConfigure(GPIO_PQ1_SSI3FSS); + MAP_GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_1); + + // + // Enable pin PF5 for SSI3 SSI3XDAT3 + // + MAP_GPIOPinConfigure(GPIO_PF5_SSI3XDAT3); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_5); + + // + // Enable pin PF0 for SSI3 SSI3XDAT1 + // + MAP_GPIOPinConfigure(GPIO_PF0_SSI3XDAT1); + MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0); + + // + // Enable pin PC7 for UART5 U5TX + // + MAP_GPIOPinConfigure(GPIO_PC7_U5TX); + MAP_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_7); + + // + // Enable pin PC6 for UART5 U5RX + // + MAP_GPIOPinConfigure(GPIO_PC6_U5RX); + MAP_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_6); + + // + // Enable pin PC5 for UART7 U7TX + // + MAP_GPIOPinConfigure(GPIO_PC5_U7TX); + MAP_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_5); + + // + // Enable pin PC4 for UART7 U7RX + // + MAP_GPIOPinConfigure(GPIO_PC4_U7RX); + MAP_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4); + + // + // Enable pin PL6 for USB0 USB0DP + // + MAP_GPIOPinTypeUSBAnalog(GPIO_PORTL_BASE, GPIO_PIN_6); + + // + // Enable pin PL7 for USB0 USB0DM + // + MAP_GPIOPinTypeUSBAnalog(GPIO_PORTL_BASE, GPIO_PIN_7); + + // + // Enable pin PB1 for USB0 USB0VBUS + // + MAP_GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_1); +} diff --git a/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin.h b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin.h new file mode 100644 index 000000000..d5e51f6b4 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin.h @@ -0,0 +1,43 @@ +//***************************************************************************** +// Copyright (c) 2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This file was automatically generated by the Tiva C Series PinMux Utility +// Version: 1.0.4 +// +//***************************************************************************** + +#ifndef __PIN_H__ +#define __PIN_H__ + +extern void PortFunctionInit(void); + +#endif // __PIN_H__ diff --git a/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin_config.c b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin_config.c new file mode 100644 index 000000000..8e378309a --- /dev/null +++ b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin_config.c @@ -0,0 +1,51 @@ +#include <stdbool.h> +#include <stdint.h> + +#include <driverlib/gpio.h> +#include <inc/hw_memmap.h> + +void InitPinOutPullUps(void) +{ + GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_INT_PIN_0,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_INT_PIN_1,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_INT_PIN_2,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_INT_PIN_3,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_INT_PIN_1,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_INT_PIN_4,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_INT_PIN_0,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_INT_PIN_1,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_INT_PIN_5,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_INT_PIN_6,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_INT_PIN_7,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_INT_PIN_2,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_INT_PIN_3,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_INT_PIN_7,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_INT_PIN_5,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTN_BASE, GPIO_INT_PIN_0,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTN_BASE, GPIO_INT_PIN_7,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTP_BASE, GPIO_INT_PIN_0,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTP_BASE, GPIO_INT_PIN_4,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTP_BASE, GPIO_INT_PIN_5,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_INT_PIN_5,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_INT_PIN_7,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTS_BASE, GPIO_INT_PIN_0,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTS_BASE, GPIO_INT_PIN_3,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTT_BASE, GPIO_INT_PIN_0,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTT_BASE, GPIO_INT_PIN_2,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD_WPU); + +} + + + + diff --git a/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin_config.h b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin_config.h new file mode 100644 index 000000000..c83281cd9 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Common/Sys_PinOut_Config/Pin_config.h @@ -0,0 +1,14 @@ +/**************************************************************************************************** + * init ialization of pull up's over GPIO + * those pins must be configured as inputs in the pinmap file by using MAP_GPIOPinTypeGPIOInput func + * here is added onlu the pull up defenition + *****************************************************************************************************/ + +#ifndef PIN_CONFIG_H_ +#define PIN_CONFIG_H_ + + +void InitPinOutPullUps(void); + + +#endif /* PIN_CONFIG_H_ */ |