Add FPGA _GPI for limit switches

8 files changed, 609 insertions, 42 deletions

diff --git a/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.c b/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.c
index 8f85903ea..7bd92ba98 100644
--- a/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.c
+++ b/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.c
@@ -26,6 +26,16 @@ Notes:
             PIN 21  - AN_IDS_PRESSENS_3
             PIN 9   - GND
 
+    J0251
+            PIN 21  - AN_IDS_PRESSENS_4
+            PIN 9   - GND
+
+                J0262
+            PIN 21  - AN_IDS_PRESSENS_6
+            PIN 9   - GND
+                        J0162
+            PIN 21  - AN_IDS_PRESSENS_5
+            PIN 9   - GND
 
 -----------------
 void ADCAcquireInit(void) // (MillisecInit) ok
@@ -37,7 +47,9 @@ uint32_t ADC_TriggerCollection(void) // MillisecLoop
 //Data Get
 void ADC0SS0Handler(void)
 
-
+each ADC there are 4 sequencers with combined sequence steps of 17 (8+4+4+1).
+Hence out of 24 channels any 17 can be mapped.
+If all channels are required then both ADC's are required (unless dynamic changes are being sought after).
 //----------------------------------------------------
 
 
@@ -120,20 +132,20 @@ uint32_t g_pui32ADCSeq[MAX_ADC_DEVICES] =
 {
  CHAN_AIR_PRESSURE_1,      //0
  CHAN_AIR_PRESSURE_2,      //1
- CHAN_DISPENSE_PRESSURE_1, //2
- CHAN_DISPENSE_PRESSURE_2, //3
- CHAN_DISPENSE_PRESSURE_3, //4
- CHAN_DISPENSE_PRESSURE_4, //5
- CHAN_DISPENSE_PRESSURE_5, //6
- CHAN_DISPENSE_PRESSURE_6, //7
- CHAN_DISPENSE_PRESSURE_7, //8
- CHAN_DISPENSE_PRESSURE_8, //9
- CHAN_VOCSENS,             //10
+ CHAN_DISPENSE_PRESSURE_1, //2      J0252 ,PIN 21  - AN_IDS_PRESSENS_1, PIN 9   - GND
+ CHAN_DISPENSE_PRESSURE_2, //3      J0142 ,PIN 21  - AN_IDS_PRESSENS_2, PIN 9   - GND
+ CHAN_DISPENSE_PRESSURE_3, //4      J0042 ,PIN 21  - AN_IDS_PRESSENS_3, PIN 9   - GND
+ CHAN_DISPENSE_PRESSURE_4, //5      J0152 ,PIN 21  - AN_IDS_PRESSENS_4, PIN 9   - GND
+ CHAN_DISPENSE_PRESSURE_5, //6      J0162 ,PIN 21  - AN_IDS_PRESSENS_5, PIN 9   - GND
+ CHAN_DISPENSE_PRESSURE_6, //7      J0262 ,PIN 21  - AN_IDS_PRESSENS_6, PIN 9   - GND
+ CHAN_DISPENSE_PRESSURE_7, //8      J0062 ,PIN 21  - AN_IDS_PRESSENS_7, PIN 9   - GND
+ CHAN_DISPENSE_PRESSURE_8, //9      J0052 ,PIN 21  - AN_IDS_PRESSENS_8, PIN 9   - GND
+ CHAN_VOCSENS,             //10     J0072 ,PIN 21  - AN_VOCSENS, PIN  9   - GND
  CHAN_SPARE1,              //11
  CHAN_SPARE2,              //12
- CHAN_LEFT_DANCER_1,       //13
- CHAN_LEFT_DANCER_2,       //14
- CHAN_RIGHT_DANCER,        //15
+ CHAN_LEFT_DANCER_1,       //13      J0002 ,PIN 21  - AN5V_LDANCER1, PIN  9   - GND
+ CHAN_LEFT_DANCER_2,       //14      J0002 ,PIN 22  - AN5V_LDANCER1, PIN 10   - GND
+ CHAN_RIGHT_DANCER,        //15      J0102 ,PIN 21  - AN5V_RDANCER, PIN 9   - GND
  CHAN_DRYER_CURRENT_1,     //16
  CHAN_DRYER_CURRENT_2,     //17
  CHAN_DRYER_CURRENT_3,     //18
@@ -230,7 +242,7 @@ void ADC0SS0Handler(void)
     MAP_ADCSequenceDataGet(ADC0_BASE, 0, &g_pui32ADCData[bufferFlipFlop][0]);
     //offset in the array calculated as sampling of 16 channels each one of 16 bits
     MAP_ADCSequenceDataGet(ADC1_BASE, 0, &g_pui32ADCData[bufferFlipFlop][8]);
-
+    MAP_ADCSequenceDataGet(ADC0_BASE, 1, &g_pui32ADCData[bufferFlipFlop][16]);
     //
     // Release adc result semaphore
     //
@@ -266,6 +278,74 @@ Void ADCProcessTask(UArg arg0, UArg arg1)
 // acquisition.
 //
 //*****************************************************************************
+//void ADCAcquireInit(void) // (called by MillisecInit)
+//{
+//    uint32_t ui32Chan, ui32Base, ui32Seq;
+//
+//    //Avaraging 8
+//    //MAP_ADCHardwareOversampleConfigure(ADC0_BASE, 8);
+//    //MAP_ADCHardwareOversampleConfigure(ADC1_BASE, 8);
+//    //
+//    // Initialize both ADC peripherals using sequencer 0 and processor trigger.
+//    //
+//    MAP_ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_PROCESSOR, 0);
+//    MAP_ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_PROCESSOR, 0);
+//
+//
+//    //
+//    // Enter loop to configure all of the ADC sequencer steps needed to
+//    // acquire the data for the data logger.  Multiple ADC and sequencers
+//    // will be used in order to acquire all the channels.
+//    //
+//    for(ui32Chan = 0; ui32Chan < MAX_ADC_DEVICES; ui32Chan++)
+//    {
+//        //
+//        // If this is the first ADC then set the base for ADC0
+//        //
+//        if(ui32Chan < 8)
+//        {
+//            ui32Base = ADC0_BASE;
+//            ui32Seq = 0;
+//        }
+//        else if(ui32Chan < 16)
+//        {
+//            //
+//            // Second ADC, set the base for ADC1
+//            //
+//            ui32Base = ADC1_BASE;
+//            ui32Seq = 0;
+//        }
+//
+//        //
+//        // Get the channel control for each channel.  Test to see if it is the
+//        // last channel for the sequencer, and if so then also set the
+//        // interrupt and "end" flags.
+//        //
+//        uint32_t ui32ChCtl = g_pui32ADCSeq[ui32Chan];
+//        //TODO define all the numbers under #define and not here
+//        if((ui32Chan == 7) || (ui32Chan == 15) || (ui32Chan == (MAX_ADC_DEVICES - 1)))
+//        {
+//            ui32ChCtl |= ADC_CTL_IE | ADC_CTL_END;
+//        }
+//
+//        //
+//        // Configure the sequence step
+//        //
+//        MAP_ADCSequenceStepConfigure(ui32Base, ui32Seq, ui32Chan % 8, ui32ChCtl);
+//    }
+//
+//    ADCReferenceSet(ADC0_BASE, ADC_REF_EXT_3V);
+//    ADCReferenceSet(ADC1_BASE, ADC_REF_EXT_3V);
+//
+//    if (!isInitialized)
+//    {
+//		// Create a periodic Clock Instance with _period - triggers the ADC sampling
+//		isInitialized = true;
+//
+//		//InitI2C();
+//    }
+//}
+
 void ADCAcquireInit(void) // (called by MillisecInit)
 {
     uint32_t ui32Chan, ui32Base, ui32Seq;
@@ -278,6 +358,8 @@ void ADCAcquireInit(void) // (called by MillisecInit)
     //
     MAP_ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_PROCESSOR, 0);
     MAP_ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_PROCESSOR, 0);
+    MAP_ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_PROCESSOR, 0);
+
 
 
     //
@@ -303,6 +385,13 @@ void ADCAcquireInit(void) // (called by MillisecInit)
             ui32Base = ADC1_BASE;
             ui32Seq = 0;
         }
+        else
+        {
+            ui32Base = ADC0_BASE;
+            ui32Seq = 1;
+        }
+
+
 
         //
         // Get the channel control for each channel.  Test to see if it is the
@@ -311,7 +400,7 @@ void ADCAcquireInit(void) // (called by MillisecInit)
         //
         uint32_t ui32ChCtl = g_pui32ADCSeq[ui32Chan];
         //TODO define all the numbers under #define and not here
-        if((ui32Chan == 7) || (ui32Chan == 15) || (ui32Chan == (MAX_ADC_DEVICES - 1)))
+        if((ui32Chan == 7) || (ui32Chan == 15)  || (ui32Chan == (MAX_ADC_DEVICES - 1)))
         {
             ui32ChCtl |= ADC_CTL_IE | ADC_CTL_END;
         }
@@ -327,10 +416,10 @@ void ADCAcquireInit(void) // (called by MillisecInit)
 
     if (!isInitialized)
     {
-		// Create a periodic Clock Instance with _period - triggers the ADC sampling
-		isInitialized = true;
+        // Create a periodic Clock Instance with _period - triggers the ADC sampling
+        isInitialized = true;
 
-		//InitI2C();
+        //InitI2C();
     }
 }
 
@@ -348,12 +437,14 @@ void ADCAcquireStart(ProcessCallback _callback, uint32_t _period) // (called by
     //
     MAP_ADCSequenceEnable(ADC0_BASE, 0);
     MAP_ADCSequenceEnable(ADC1_BASE, 0);
+    MAP_ADCSequenceEnable(ADC0_BASE, 1);
 
     //
     // Flush the ADC sequencers to be sure there is no lingering/ trush data.
     //
     MAP_ADCSequenceDataGet(ADC0_BASE, 0, g_pui32ADCData[0]);
     MAP_ADCSequenceDataGet(ADC1_BASE, 0, g_pui32ADCData[0]);
+    MAP_ADCSequenceDataGet(ADC1_BASE, 1, g_pui32ADCData[0]);
 
     //
     // Enable ADC interrupts
diff --git a/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.h b/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.h
index 54a0c595f..ac017c7a7 100644
--- a/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.h
+++ b/Software/Embedded_SW/Embedded/Drivers/ADC_Sampling/ADC.h
@@ -63,4 +63,6 @@ void ADCAcquireStart(ProcessCallback _callback, uint32_t _period);
 
 void ADCAcquireStop(void);
 
+void ADC0SS0Handler(void);
+
 #endif /* DRIVERS_ADC_H_ */
diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c
index 290f93353..50b3d627e 100644
--- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c
+++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c
@@ -164,16 +164,18 @@ void FPGA_Init()
 
 //---------------------------------- Limit_Switches ------------------------------------------------
 
-Limit_Switch1_REG   Limit_Switch1;
-Limit_Switch2_REG   Limit_Switch2;
-Limit_Switch3_REG   Limit_Switch3;
+//Limit_Switch1_REG   Limit_Switch1;
+//Limit_Switch2_REG   Limit_Switch2;
+//Limit_Switch3_REG   Limit_Switch3;
+//
+//void FPGA_Read_limit_Switches()
+//{
+//    Limit_Switch1.ushort = F1_GPI_LS1_D;
+//    Limit_Switch2.ushort = F1_GPI_LS2_D;
+//    Limit_Switch3.ushort = F1_GPI_LS3_D;
+//}
+
 
-void FPGA_Read_limit_Switches()
-{
-    Limit_Switch1.ushort = F1_GPI_LS1_D;
-    Limit_Switch2.ushort = F1_GPI_LS2_D;
-    Limit_Switch3.ushort = F1_GPI_LS3_D;
-}
 
 
 
diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h
index 661ff46ca..531eae734 100644
--- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h
+++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h
@@ -5,7 +5,7 @@ int FPGA_Test();
 int FPGA_Test_ReadBack(unsigned char FPGA_NUM, unsigned short Value, unsigned short *ReadBackValue);
 int  FPGA_ReadVersion(unsigned char FPGA_NUM, unsigned char *Version, unsigned char *Year, unsigned char *Month, unsigned char *Day);
 void FPGA_Init();
-void FPGA_Read_limit_Switches(void);
+//void FPGA_Read_limit_Switches(void);
 
 
 #endif //FPGA_H
diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h
index b9f767bc2..49da97aa5 100644
--- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h
+++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h
@@ -294,19 +294,19 @@
 #define F2_Ver2_D                              (*((volatile short  *)(FPGA2_BASE | 0x010)))    //Version of Fpga is held here
 
 //GPI shorterrupt LS_01 Registers
-#define F2_GPI_LS1_D                           (*((volatile short  *)(FPGA2_BASE | 0x020)))    //Reads the direct values that are currently being sent to the fpga.
-#define F2_GPI_LS1_L                           (*((volatile short  *)(FPGA2_BASE | 0x022)))    //Value of the latched shorterrupts that have occurred
-#define F2_GPI_LS1_M                           (*((volatile short  *)(FPGA2_BASE | 0x024)))    //Value of the shorterrupt mask, Default is 0x0000
+#define F2_LS_01_Direct                        (*((volatile short  *)(FPGA2_BASE | 0x020)))    //Reads the direct values that are currently being sent to the fpga.
+#define F2_LS_01_Latched                       (*((volatile short  *)(FPGA2_BASE | 0x022)))    //Value of the latched shorterrupts that have occurred
+#define F2_LS_01_Mask                          (*((volatile short  *)(FPGA2_BASE | 0x024)))    //Value of the shorterrupt mask, Default is 0x0000
 
 //GPI shorterrupt LS_02 Registers
-#define F2_GPI_LS2_D                           (*((volatile short  *)(FPGA2_BASE | 0x030)))    //Reads the direct values that are currently being sent to the fpga.
-#define F2_GPI_LS2_L                           (*((volatile short  *)(FPGA2_BASE | 0x032)))    //Value of the latched shorterrupts that have occurred
-#define F2_GPI_LS2_M                           (*((volatile short  *)(FPGA2_BASE | 0x034)))    //Value of the shorterrupt mask, Default is 0x0000
+#define F2_LS_02_Direct                        (*((volatile short  *)(FPGA2_BASE | 0x030)))    //Reads the direct values that are currently being sent to the fpga.
+#define F2_LS_02_Latched                       (*((volatile short  *)(FPGA2_BASE | 0x032)))    //Value of the latched shorterrupts that have occurred
+#define F2_LS_02_Mask                          (*((volatile short  *)(FPGA2_BASE | 0x034)))    //Value of the shorterrupt mask, Default is 0x0000
 
 //GPI shorterrupt LS_03 Registers
-#define F2_GPI_LS3_D                           (*((volatile short  *)(FPGA2_BASE | 0x040)))     //Reads the direct values that are currently being sent to the fpga.
-#define F2_GPI_LS3_L                           (*((volatile short  *)(FPGA2_BASE | 0x042)))     //Value of the latched shorterrupts that have occurred
-#define F2_GPI_LS3_M                           (*((volatile short  *)(FPGA2_BASE | 0x044)))     //Value of the shorterrupt mask, Default is 0x0000
+#define F2_LS_03_Direct                        (*((volatile short  *)(FPGA2_BASE | 0x040)))     //Reads the direct values that are currently being sent to the fpga.
+#define F2_LS_03_Latched                       (*((volatile short  *)(FPGA2_BASE | 0x042)))     //Value of the latched shorterrupts that have occurred
+#define F2_LS_03_Mask                          (*((volatile short  *)(FPGA2_BASE | 0x044)))     //Value of the shorterrupt mask, Default is 0x0000
 
 //Moto_Driver_NBUSY_register1
 #define F2_Moto_Driver_NBUSY1_D                (*((volatile short  *)(FPGA2_BASE | 0x050)))     //Reads the direct values that are currently being sent to the fpga.
@@ -1120,7 +1120,7 @@ typedef union
 
 
 //---------------------------------- Limit_Switches ------------------------------------------------
-
+/*
 //F1_GPI_LS1_D
 typedef union
 {
@@ -1180,8 +1180,8 @@ typedef union
         bool F1_LS_SCREW_LEFT      : 1; //1
         bool F1_LS_RSPARE2         : 1; //2
         bool F1_LS_RSPARE1         : 1; //3
-        bool F1_LS_RDANCER_LONG    : 1; //4 (F1_LS_RLOADRAM_UP)
-        bool F1_LS_RLOADRAM_DOWN   : 1; //5
+        bool F1_LS_RLOADRAM_UP     : 1; //4
+        bool F1_LS_RDANCER_LONG    : 1; //5 (F1_LS_RLOADRAM_DOWN)
         bool F1_LS_RLOADMOTOR_UP   : 1; //6
         bool F1_LS_RLOADMOTOR_DOWN : 1; //7
         bool F1_LS_RDANCER_UP      : 1; //8
@@ -1195,7 +1195,7 @@ typedef union
     }bits;
     unsigned short ushort;
 }Limit_Switch3_REG;
-
+*/
 //------------------------------------ SSR ----------------------------------------
 
 //F2_CTRL
@@ -1243,6 +1243,168 @@ typedef union
 }F2_CTRL_SSR_REG;
 
 */
+//--------------------------------------------------------------------------------
+
+
+//F1_LS_01_Direct
+typedef union
+{
+    struct
+    {
+        bool F1_LS_DRYER_SPARE4     : 1; //0
+        bool F1_LS_DRYER_SPARE3     : 1; //1
+        bool F1_LS_DRYER_SPARE2     : 1; //2
+        bool F1_LS_DRYER_SPARE1     : 1; //3
+        bool F1_LS_DRYER_LID_OPEN   : 1; //4
+        bool F1_LS_DRYER_LID_CLOSED : 1; //5
+        bool F1_LS_DH_SPARE2        : 1; //6
+        bool F1_LS_DH_LID_OPEN      : 1; //7
+        bool F1_LS_DH_LID_CLOSED    : 1; //8
+        bool F1_LS_DH_LID_CLEANING  : 1; //9
+        bool F1_LS_DH_CLEAN_UP      : 1; //10
+        bool F1_LS_DH_CLEAN_RIGHT   : 1; //11
+        bool F1_LS_DH_CLEAN_LEFT    : 1; //12
+        bool F1_LS_DH_CLEAN_DOWN    : 1; //13
+        unsigned char RESERVE       : 2; //14-15
+    }bits;
+    unsigned short ushort;
+}LS_DRYER_DH;
+
+//F1_LS_02_Direct
+typedef union
+{
+    struct
+    {
+        bool F1_LS_PIVOT_SPARE2    : 1; //0
+        bool F1_LS_PIVOT_SPARE1    : 1; //1
+        bool F1_LS_LSPARE2         : 1; //2
+        bool F1_LS_LSPARE1         : 1; //3
+        bool F1_LS_LPIVOT_UP       : 1; //4
+        bool F1_LS_LPIVOT_DOWN     : 1; //5
+        bool F1_LS_LOADARM_RIGHT   : 1; //6
+        bool F1_LS_LOADARM_LEFT    : 1; //7
+        bool F1_LS_LLOADMOTOR_UP   : 1; //8
+        bool F1_LS_LLOADMOTOR_DOWN : 1; //9
+        bool F1_LS_LDANCER2_UP     : 1; //10
+        bool F1_LS_LDANCER2_DOWN   : 1; //11
+        bool F1_LS_LDANCER1_UP     : 1; //12
+        bool F1_LS_LDANCER1_DOWN   : 1; //13
+        unsigned char RESERVE      : 2; //14-15
+    }bits;
+    unsigned short ushort;
+}LS_LEFT;
+
+//F1_LS_03_Direct
+typedef union
+{
+    struct
+    {
+        bool F1_LS_SCREW_RIGHT     : 1; //0
+        bool F1_LS_SCREW_LEFT      : 1; //1
+        bool F1_LS_RSPARE2         : 1; //2
+        bool F1_LS_RSPARE1         : 1; //3
+        bool F1_LS_RLOADRAM_UP     : 1; //4
+        bool F1_LS_RDANCER_LONG    : 1; //5 // F1_LS_RLOADRAM_DOWN
+        bool F1_LS_RLOADMOTOR_UP   : 1; //6
+        bool F1_LS_RLOADMOTOR_DOWN : 1; //7
+        bool F1_LS_RDANCER_UP      : 1; //8
+        bool F1_LS_RDANCER_DOWN    : 1; //9
+        bool F1_SW_SPARE           : 1; //10
+        bool F1_SW_SPOOL_EXISTS    : 1; //11
+        unsigned char RESERVE      : 4; //12-15
+    }bits;
+    unsigned short ushort;
+}LS_RIGHT_SCREW_SPOOL;
+
+//F2_LS_01_Direct
+typedef union
+{
+    struct
+    {
+        bool F2_LS_DISPENSER_SPARE_1 : 1; //0
+        bool F2_LS_DISPENSER_50_1    : 1; //1
+        bool F2_LS_DISPENSER_DOWN_1  : 1; //2
+        bool F2_LS_DISPENSER_75_1    : 1; //3
+        bool F2_LS_DISPENSER_25_1    : 1; //4
+        bool F2_LS_DISPENSER_UP_1    : 1; //5
+        bool F2_LS_DISPENSER_SPARE_2 : 1; //6
+        bool F2_LS_DISPENSER_50_2    : 1; //7
+        bool F2_LS_DISPENSER_DOWN_2  : 1; //8
+        bool F2_LS_DISPENSER_75_2    : 1; //9
+        bool F2_LS_DISPENSER_25_2    : 1; //10
+        bool F2_LS_DISPENSER_UP_2    : 1; //11
+        unsigned char RESERVE        : 4; //12-15
+    }bits;
+    unsigned short ushort;
+}LS_DISPENSER_1_2;
+
+//F2_LS_02_Direct
+typedef union
+{
+    struct
+    {
+        bool F2_LS_DISPENSER_SPARE_3 : 1; //0
+        bool F2_LS_DISPENSER_50_3    : 1; //1
+        bool F2_LS_DISPENSER_DOWN_3  : 1; //2
+        bool F2_LS_DISPENSER_75_3    : 1; //3
+        bool F2_LS_DISPENSER_25_3    : 1; //4
+        bool F2_LS_DISPENSER_UP_3    : 1; //5
+        bool F2_LS_DISPENSER_SPARE_4 : 1; //6
+        bool F2_LS_DISPENSER_50_4    : 1; //7
+        bool F2_LS_DISPENSER_DOWN_4  : 1; //8
+        bool F2_LS_DISPENSER_75_4    : 1; //9
+        bool F2_LS_DISPENSER_25_4    : 1; //10
+        bool F2_LS_DISPENSER_UP_4    : 1; //11
+        unsigned char RESERVE        : 4; //12-15
+    }bits;
+    unsigned short ushort;
+}LS_DISPENSER_3_4;
+
+
+//F2_LS_03_Direct
+typedef union
+{
+    struct
+    {
+        bool F2_LS_DISPENSER_SPARE_5 : 1; //0
+        bool F2_LS_DISPENSER_50_5    : 1; //1
+        bool F2_LS_DISPENSER_DOWN_5  : 1; //2
+        bool F2_LS_DISPENSER_75_5    : 1; //3
+        bool F2_LS_DISPENSER_25_5    : 1; //4
+        bool F2_LS_DISPENSER_UP_5    : 1; //5
+        bool F2_LS_DISPENSER_SPARE_6 : 1; //6
+        bool F2_LS_DISPENSER_50_6    : 1; //7
+        bool F2_LS_DISPENSER_DOWN_6  : 1; //8
+        bool F2_LS_DISPENSER_75_6    : 1; //9
+        bool F2_LS_DISPENSER_25_6    : 1; //10
+        bool F2_LS_DISPENSER_UP_6    : 1; //11
+        unsigned char RESERVE        : 4; //12-15
+    }bits;
+    unsigned short ushort;
+}LS_DISPENSER_5_6;
+
+//F2_LS_04_Direct
+typedef union
+{
+    struct
+    {
+        bool F2_LS_DISPENSER_SPARE_7 : 1; //0
+        bool F2_LS_DISPENSER_50_7    : 1; //1
+        bool F2_LS_DISPENSER_DOWN_7  : 1; //2
+        bool F2_LS_DISPENSER_75_7    : 1; //3
+        bool F2_LS_DISPENSER_25_7    : 1; //4
+        bool F2_LS_DISPENSER_UP_7    : 1; //5
+        bool F2_LS_DISPENSER_SPARE_8 : 1; //6
+        bool F2_LS_DISPENSER_50_8    : 1; //7
+        bool F2_LS_DISPENSER_DOWN_8  : 1; //8
+        bool F2_LS_DISPENSER_75_8    : 1; //9
+        bool F2_LS_DISPENSER_25_8    : 1; //10
+        bool F2_LS_DISPENSER_UP_8    : 1; //11
+        unsigned char RESERVE        : 4; //12-15
+    }bits;
+    unsigned short ushort;
+}LS_DISPENSER_7_8;
+
 
 //------------------------------ MOTOR DRIVER L_6470 ------------------------------
 
diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c
new file mode 100644
index 000000000..a785bbbfb
--- /dev/null
+++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c
@@ -0,0 +1,146 @@
+/*
+ * FPGA_GPIO.c
+ *
+ *  Created on: May 30, 2018
+ *      Author: avi
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <drivers/FPGA/FPGA_Comm.h>
+#include <DataDef.h>
+
+#include "modules/control/millisecTask.h"
+#include "modules/thread/thread.h"
+
+#include "FPGA_GPIO.h"
+
+FPGA_GPI FPGA_Gpi;
+
+bool FPGA_Gpi_Buf[MAX_GPI] = {0};
+
+void Read_FPGA_GPI_Rgisters()
+{
+    uint32_t i;
+    unsigned char index_buf;
+    unsigned shift;
+    unsigned char Size = sizeof(unsigned short) * 8; // register from the FPGA is 16 bit
+
+    FPGA_Gpi.Reg.GPI_LS1_D = F1_GPI_LS1_D;
+    FPGA_Gpi.Reg.GPI_LS2_D = F1_GPI_LS2_D;
+    FPGA_Gpi.Reg.GPI_LS3_D = F1_GPI_LS3_D;
+
+    FPGA_Gpi.Reg.LS_01 = F2_LS_01_Direct;
+    FPGA_Gpi.Reg.LS_01 = F2_LS_01_Direct;
+    FPGA_Gpi.Reg.LS_01 = F2_LS_01_Direct;
+    FPGA_Gpi.Reg.LS_01 = F2_LS_01_Direct;
+
+   for(i=0;i<MAX_GPI;i++)
+   {
+       index_buf = i / Size;
+       shift  = i % Size;
+
+       FPGA_Gpi_Buf[i] = (FPGA_Gpi.Buf[index_buf] & (0x01 << shift)) >> shift;
+   }
+}
+
+
+
+/* example to read the Limit switch :
+
+if(FPGA_Gpi_Buf[GPI_LS_RLOADRAM_UP] == LIMIT)
+{
+      // stop motor
+}
+*/
+
+void test_fpga_gpi()
+{
+    bool nop = false;
+
+    Read_FPGA_GPI_Rgisters();
+
+    if(     FPGA_Gpi_Buf[GPI_LS_LPIVOT_UP]       |
+            FPGA_Gpi_Buf[GPI_LS_LPIVOT_DOWN]     |
+            FPGA_Gpi_Buf[GPI_LS_LLOADMOTOR_UP]   |
+            FPGA_Gpi_Buf[GPI_LS_LLOADMOTOR_DOWN] |
+            FPGA_Gpi_Buf[GPI_LS_LDANCER1_UP]     |
+            FPGA_Gpi_Buf[GPI_LS_LDANCER1_DOWN]   |
+
+            FPGA_Gpi_Buf[GPI_LS_RDANCER_LONG]    |
+            FPGA_Gpi_Buf[GPI_LS_RLOADMOTOR_UP]   |
+            FPGA_Gpi_Buf[GPI_LS_RLOADMOTOR_DOWN] |
+            FPGA_Gpi_Buf[GPI_LS_RDANCER_UP]      |
+            FPGA_Gpi_Buf[GPI_LS_RDANCER_DOWN]
+                          == LIMIT)
+    {
+        nop = true;
+    }
+
+}
+
+LS_LEFT LS_Left;
+LS_RIGHT_SCREW_SPOOL Ls_Right_Screw_Spool;
+
+void FPGA_Read_limit_Switches_Registers()
+{
+    LS_Left.ushort              = F1_GPI_LS2_D;
+    Ls_Right_Screw_Spool.ushort = F1_GPI_LS3_D;
+}
+
+bool FPGA_Read_limit_Switches(FPGA_GPI_ENUM Limit_Switch)
+{
+    bool LM_Status = NO_LIMIT;
+
+    switch(Limit_Switch)
+    {
+        case GPI_LS_LPIVOT_UP:
+            LM_Status = LS_Left.bits.F1_LS_LPIVOT_UP;
+            break;
+        case GPI_LS_LPIVOT_DOWN:
+            LM_Status = LS_Left.bits.F1_LS_LPIVOT_DOWN;
+            break;
+        case GPI_LS_LLOADMOTOR_UP:
+            LM_Status = LS_Left.bits.F1_LS_LLOADMOTOR_UP;
+            break;
+        case GPI_LS_LLOADMOTOR_DOWN:
+            LM_Status = LS_Left.bits.F1_LS_LLOADMOTOR_DOWN;
+            break;
+        case GPI_LS_LDANCER1_UP:
+            LM_Status = LS_Left.bits.F1_LS_LDANCER1_UP;
+            break;
+        case GPI_LS_LDANCER1_DOWN:
+            LM_Status = LS_Left.bits.F1_LS_LDANCER1_DOWN;
+            break;
+        case GPI_LS_RDANCER_LONG:
+            LM_Status = Ls_Right_Screw_Spool.bits.F1_LS_RDANCER_LONG;
+            break;
+        case GPI_LS_RLOADMOTOR_UP:
+            LM_Status = Ls_Right_Screw_Spool.bits.F1_LS_RLOADMOTOR_UP;
+            break;
+        case GPI_LS_RLOADMOTOR_DOWN:
+            LM_Status = Ls_Right_Screw_Spool.bits.F1_LS_RLOADMOTOR_DOWN;
+            break;
+        case GPI_LS_RDANCER_UP:
+            LM_Status = Ls_Right_Screw_Spool.bits.F1_LS_RDANCER_UP;
+            break;
+        case GPI_LS_RDANCER_DOWN:
+            LM_Status = Ls_Right_Screw_Spool.bits.F1_LS_RDANCER_DOWN;
+            break;
+
+        case GPI_LS_SCREW_RIGHT:
+            LM_Status = Ls_Right_Screw_Spool.bits.F1_LS_SCREW_RIGHT;
+            break;
+        case GPI_LS_SCREW_LEFT:
+            LM_Status = Ls_Right_Screw_Spool.bits.F1_LS_SCREW_LEFT;
+            break;
+
+        default :
+                //error
+            break;
+    }
+    return LM_Status;
+}
+
+
+
diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h
new file mode 100644
index 000000000..6633e5f46
--- /dev/null
+++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h
@@ -0,0 +1,164 @@
+/*
+ * FPGA_GPIO.h
+ *
+ *  Created on: May 30, 2018
+ *      Author: avi
+ */
+
+#ifndef DRIVERS_FPGA_FPGA_GPIO_FPGA_GPIO_H_
+#define DRIVERS_FPGA_FPGA_GPIO_FPGA_GPIO_H_
+
+typedef enum
+{
+    //F1_LS_01_Direct
+    GPI_LS_DRYER_SPARE4,        //0
+    GPI_LS_DRYER_SPARE3,        //1
+    GPI_LS_DRYER_SPARE2,        //2
+    GPI_LS_DRYER_SPARE1,        //3
+    GPI_LS_DRYER_LID_OPEN,      //4
+    GPI_LS_DRYER_LID_CLOSED,    //5
+    GPI_LS_DH_SPARE2,           //6
+    GPI_LS_DH_LID_OPEN,         //7
+    GPI_LS_DH_LID_CLOSED,       //8
+    GPI_LS_DH_LID_CLEANING,     //9
+    GPI_LS_DH_CLEAN_UP,         //10
+    GPI_LS_DH_CLEAN_RIGHT,      //11
+    GPI_LS_DH_CLEAN_LEFT,       //12
+    GPI_LS_DH_CLEAN_DOWN,       //13
+    GPI_F1_LS_01_Direct_BIT14,  //14
+    GPI_F1_LS_01_Direct_BIT15,  //15
+
+    //F1_LS_02_Direct
+    GPI_LS_PIVOT_SPARE2,        //16
+    GPI_LS_PIVOT_SPARE1,        //17
+    GPI_LS_LSPARE2,             //18
+    GPI_LS_LSPARE1,             //19
+    GPI_LS_LPIVOT_UP,           //20
+    GPI_LS_LPIVOT_DOWN,         //21
+    GPI_LS_LOADARM_RIGHT,       //22
+    GPI_LS_LOADARM_LEFT,        //23
+    GPI_LS_LLOADMOTOR_UP,       //24
+    GPI_LS_LLOADMOTOR_DOWN,     //25
+    GPI_LS_LDANCER2_UP,         //26
+    GPI_LS_LDANCER2_DOWN,       //27
+    GPI_LS_LDANCER1_UP,         //28
+    GPI_LS_LDANCER1_DOWN,       //29
+    GPI_F1_LS_02_Direct_BIT14,  //30
+    GPI_F1_LS_02_Direct_BIT15,  //31
+
+    //F1_LS_03_Direct
+    GPI_LS_SCREW_RIGHT,         //32
+    GPI_LS_SCREW_LEFT,          //33
+    GPI_LS_RSPARE2,             //34
+    GPI_LS_RSPARE1,             //35
+    GPI_LS_RLOADRAM_UP,         //36
+    GPI_LS_RDANCER_LONG,        //37 //GPI_LS_RLOADRAM_DOWN
+    GPI_LS_RLOADMOTOR_UP,       //38
+    GPI_LS_RLOADMOTOR_DOWN,     //39
+    GPI_LS_RDANCER_UP,          //40
+    GPI_LS_RDANCER_DOWN,        //41
+    GPI_SW_SPARE,               //42
+    GPI_SW_SPOOL_EXISTS,        //43
+    GPI_F1_LS_03_Direct_BIT12,  //44
+    GPI_F1_LS_03_Direct_BIT13,  //45
+    GPI_F1_LS_03_Direct_BIT14,  //46
+    GPI_F1_LS_03_Direct_BIT15,  //47
+
+    //LS_01_Direct
+    GPI_LS_DISPENSER_SPARE_1,   //48
+    GPI_LS_DISPENSER_50_1,      //49
+    GPI_LS_DISPENSER_DOWN_1,    //50
+    GPI_LS_DISPENSER_75_1,      //51
+    GPI_LS_DISPENSER_25_1,      //52
+    GPI_LS_DISPENSER_UP_1,      //53
+    GPI_LS_DISPENSER_SPARE_2,   //54
+    GPI_LS_DISPENSER_50_2,      //55
+    GPI_LS_DISPENSER_DOWN_2,    //56
+    GPI_LS_DISPENSER_75_2,      //57
+    GPI_LS_DISPENSER_25_2,      //58
+    GPI_LS_DISPENSER_UP_2,      //59
+    GPI_LS_01_Direct_BIT12,     //60
+    GPI_LS_01_Direct_BIT13,     //61
+    GPI_LS_01_Direct_BIT14,     //62
+    GPI_LS_01_Direct_BIT15,     //63
+
+    //LS_02_Direct
+    GPI_LS_DISPENSER_SPARE_3,   //64
+    GPI_LS_DISPENSER_50_3,      //65
+    GPI_LS_DISPENSER_DOWN_3,    //66
+    GPI_LS_DISPENSER_75_3,      //67
+    GPI_LS_DISPENSER_25_3,      //68
+    GPI_LS_DISPENSER_UP_3,      //69
+    GPI_LS_DISPENSER_SPARE_4,   //70
+    GPI_LS_DISPENSER_50_4,      //71
+    GPI_LS_DISPENSER_DOWN_4,    //72
+    GPI_LS_DISPENSER_75_4,      //73
+    GPI_LS_DISPENSER_25_4,      //74
+    GPI_LS_DISPENSER_UP_4,      //75
+    GPI_LS_02_Direct_BIT12,     //76
+    GPI_LS_02_Direct_BIT13,     //77
+    GPI_LS_02_Direct_BIT14,     //78
+    GPI_LS_02_Direct_BIT15,     //79
+
+    //LS_03_Direct
+    GPI_LS_DISPENSER_SPARE_5,    //80
+    GPI_LS_DISPENSER_50_5,       //81
+    GPI_LS_DISPENSER_DOWN_5,     //82
+    GPI_LS_DISPENSER_75_5,       //83
+    GPI_LS_DISPENSER_25_5,       //84
+    GPI_LS_DISPENSER_UP_5,       //85
+    GPI_LS_DISPENSER_SPARE_6,    //86
+    GPI_LS_DISPENSER_50_6,       //87
+    GPI_LS_DISPENSER_DOWN_6,     //88
+    GPI_LS_DISPENSER_75_6,       //89
+    GPI_LS_DISPENSER_25_6,       //90
+    GPI_LS_DISPENSER_UP_6,       //91
+    GPI_LS_03_Direct_BIT12,      //92
+    GPI_LS_03_Direct_BIT13,      //93
+    GPI_LS_03_Direct_BIT14,      //94
+    GPI_LS_03_Direct_BIT15,      //95
+
+    //LS_04_Direct
+    GPI_LS_DISPENSER_SPARE_7,    //96
+    GPI_LS_DISPENSER_50_7,       //97
+    GPI_LS_DISPENSER_DOWN_7,     //98
+    GPI_LS_DISPENSER_75_7,       //99
+    GPI_LS_DISPENSER_25_7,       //100
+    GPI_LS_DISPENSER_UP_7,       //101
+    GPI_LS_DISPENSER_SPARE_8,    //102
+    GPI_LS_DISPENSER_50_8,       //103
+    GPI_LS_DISPENSER_DOWN_8,     //104
+    GPI_LS_DISPENSER_75_8,       //105
+    GPI_LS_DISPENSER_25_8,       //106
+    GPI_LS_DISPENSER_UP_8,       //107
+    GPI_LS_04_Direct_BIT12,      //108
+    GPI_LS_04_Direct_BIT13,      //109
+    GPI_LS_04_Direct_BIT14,      //110
+    GPI_LS_04_Direct_BIT15,      //111
+
+    //-----------------------
+    MAX_GPI
+}FPGA_GPI_ENUM;
+
+typedef union
+{
+    struct
+    {
+        unsigned short GPI_LS1_D;
+        unsigned short GPI_LS2_D;
+        unsigned short GPI_LS3_D;
+        unsigned short LS_01;
+        unsigned short LS_02;
+        unsigned short LS_03;
+        unsigned short LS_04;
+    }Reg;
+    unsigned short Buf[MAX_GPI/sizeof(unsigned short)];
+}FPGA_GPI;
+
+extern bool FPGA_Gpi_Buf[MAX_GPI];
+
+void Read_FPGA_GPI_Rgisters();
+
+
+
+#endif /* DRIVERS_FPGA_FPGA_GPIO_FPGA_GPIO_H_ */
diff --git a/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h b/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h
index ee043bee6..847677202 100644
--- a/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h
+++ b/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h
@@ -141,7 +141,7 @@ typedef enum
     GPI131_LS_RDANCER_DOWN,
     GPI132_LS_RDANCER_UP,
     GPI133_LS_RLOADMOTOR_DOWN,
-    GPI134_LS_RLOADRAM_DOWN,
+    GPI134_LS_RLOADRAM_DOWN, //F1_LS_RDANCER_LONG
     GPI135_LS_RLOADRAM_UP,
     GPI136_LS_RSPARE1,
     GPI137_LS_RSPARE2,