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| author | Avi Levkovich <avi@twine-s.com> | 2019-11-19 13:33:51 +0200 |
|---|---|---|
| committer | Avi Levkovich <avi@twine-s.com> | 2019-11-19 13:33:51 +0200 |
| commit | b5ea623d1ea2cef2e117c12eaf4cd66351c42cce (patch) | |
| tree | ff15a121e57afc6cf4f017bcc2d4d6a7cc7dd78d /Software/Embedded_SW/Embedded | |
| parent | d87f59593916413b747ebe15f409ec09007747a3 (diff) | |
| parent | d50797ddb8c3d886d38a56a09dfe34540512e331 (diff) | |
| download | Tango-b5ea623d1ea2cef2e117c12eaf4cd66351c42cce.tar.gz Tango-b5ea623d1ea2cef2e117c12eaf4cd66351c42cce.zip | |
Merge branch 'master' of https://twinetfs.visualstudio.com/_git/Tango
Diffstat (limited to 'Software/Embedded_SW/Embedded')
20 files changed, 3150 insertions, 26 deletions
diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/Head_Card/I2C_Head_Mux.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/Head_Card/I2C_Head_Mux.h index 12eacfedb..24eb5bfe7 100644 --- a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/Head_Card/I2C_Head_Mux.h +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/Head_Card/I2C_Head_Mux.h @@ -41,5 +41,6 @@ The I2C addresses on the board: uint32_t Select_Main_Head_Mux_Channel(); uint32_t Select_Main_Head_Mux_Channel_test();//test via the dispenser card connected to dispenser 0 +uint32_t Block_Main_Head_Mux_Channel(); #endif /* DRIVERS_I2C_COMMUNICATION_HEAD_CARD_I2C_HEAD_MUX_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_EMC2302_fan.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_EMC2302_fan.c new file mode 100644 index 000000000..abb62531c --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_EMC2302_fan.c @@ -0,0 +1,346 @@ +/* + * fan_click.c + * + * Created on: Oct 27, 2019 + * Author: avi + * + * STUB: haed_card_fan_test + * var response = stubManager.Run<ProgressResponse>("ProgressRequest" ,0xfac, 0x00);//Fan Click WHS Card , Fan 1 Setting - 0xFF Full PWM 0x80 = 50% FF = 100% 0 - STOP + * stubManager.WriteLineHex(response.Progress,2);//100% = 0xDC0, 50% = 0x1790, 0% = 0xFFF0 + */ + +/****************************************************************************** +* Includes +*******************************************************************************/ +#include "include.h" +#include "../I2C_WHS_Mux.h" +#include <Drivers/I2C_Communication/I2C.h> +#include <Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_EMC2302_fan.h> +#include <Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_Fan.h> + +uint8_t D_Fan_PWM_Output_Config (uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr); +uint8_t D_Fan_Setting (uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr, bool Fan); +uint8_t D_Fan_Read_Tacho (uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr, bool Fan); +uint8_t D_fan_click_productID (uint8_t EMC2302_I2C_bus_number , uint8_t EMC2302_I2C_addr); +uint8_t D_fan_click_manufactuerID (uint8_t EMC2302_I2C_bus_number , uint8_t EMC2302_I2C_addr); +uint8_t D_fan_click_revision (uint8_t EMC2302_I2C_bus_number , uint8_t EMC2302_I2C_addr); +uint8_t D_Read_Config_Reg (uint8_t EMC2302_I2C_bus_number , uint8_t EMC2302_I2C_addr); +uint8_t D_Fan_config (uint8_t EMC2302_I2C_bus_number , uint8_t EMC2302_I2C_addr); + + +/****************************************************************************** +* Module Variable Definitions +*******************************************************************************/ +uint8_t readbuffer[2]; +uint8_t writebuffer[2]; + + +//uint32_t I2C_FAN_SLAVE_ADD = 0x5C; + + +FAN_CLICK_INFO Fan_Click_Info; + +uint16_t Fan_Tach[2] = {0,0}; +uint8_t D_Fan_PWM_Command[2] = {0,0}; + + + +EMC2302_READ EMC2302_Read; + + + +EMC2302_WRITE EMC2302_Write; + +uint8_t D_EMC2302_Reg_Add[EMC2302_Size] = { +0x20,0x24,0x25,0x26,0x27,0x29,0x2A,0x2B,0x2D, +0x30,0x40,0x31,0x41,0x32,0x42,0x33,0x43,0x35,0x45,0x36,0x46,0x37,0x47,0x38,0x48,0x39,0x49,0x3A,0x4A,0x3B,0x4B,0x3C,0x4C,0x3D,0x4D,0x3E,0x4E,0x3F,0x4F, +0xEF,0xFD,0xFE,0xFF}; + +/****************************************************************************** +* Function Definitions +*******************************************************************************/ + + + + +//uint8_t D_Fan_PWM_Polarity_Config() +//{ +// uint8_t status = ERROR; +// +// if(EMC2302_Write.Reg.PWM_Polarity_Config <=0x03)//Bit0 invert PWM1, Bit2 invert PWM2 +// { +// writebuffer[0] = EMC2301_PWM_POLARITY; +// writebuffer[1] = EMC2302_Write.Reg.PWM_Polarity_Config;; +// status = I2C_Write(I2C_ID_WHS_CARD, I2C_WHS_FAN_SLAVE_ADD, writebuffer, 2); +// } +// return status; +//} + + + +//uint8_t WHS_Fan_PWM_Base_Frequency() +//{ +// uint8_t status = ERROR; +// +// if( EMC2302_Write.Reg.PWM_Base_Freq <= ((FAN_FREQ_2_441HZ << 2) | FAN_FREQ_2_441HZ)) +// { +// writebuffer[0] = EMC2301_PWM_BASE_FREQ; +// writebuffer[1] = EMC2302_Write.Reg.PWM_Base_Freq; +// status = I2C_Write(I2C_ID_WHS_CARD, I2C_WHS_FAN_SLAVE_ADD, writebuffer, 2); +// } +// return status; +//} + + + + +/******************************************* + ******** Informational Functions ********** + ******************************************/ + + +uint8_t D_fan_click_productID(uint8_t EMC2302_I2C_bus_number, uint8_t EMC2302_I2C_addr) +{ + uint8_t status = OK; + writebuffer[0] = EMC2301_PRODUCT_ID; + readbuffer[0] = 0; + status |= I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + Fan_Click_Info.Product_ID = readbuffer[0]; + return status; +} + +uint8_t D_fan_click_manufactuerID(uint8_t EMC2302_I2C_bus_number, uint8_t EMC2302_I2C_addr) +{ + uint8_t status = OK; + writebuffer[0] = EMC2301_MANUFACTUERE_ID; + status |= I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + Fan_Click_Info.Product_ID = readbuffer[0]; + return status; +} + +uint8_t D_fan_click_revision(uint8_t EMC2302_I2C_bus_number, uint8_t EMC2302_I2C_addr) +{ + uint8_t status = OK; + writebuffer[0] = EMC2301_REVISION; + status |= I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + Fan_Click_Info.Product_ID = readbuffer[0]; + return status; +} + +uint8_t D_Read_Config_Reg(uint8_t EMC2302_I2C_bus_number, uint8_t EMC2302_I2C_addr) +{ + uint8_t status = OK; + writebuffer[0] = EMC2301_CONFIGURATION; + status |= I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + + EMC2302_Read.Reg.Configuration = readbuffer[0]; + + return status; +} + +//uint8_t WHS_Fan_Read_Register(uint8_t Reg) +//{ +// uint8_t status = OK; +// writebuffer[0] = Reg; +// status |= I2C_Write(I2C_ID_WHS_CARD, I2C_WHS_FAN_SLAVE_ADD, writebuffer, 1); +// delayUs(10);//TODO - check the delay +// status |= I2C_Read(I2C_ID_WHS_CARD, I2C_WHS_FAN_SLAVE_ADD + 1, readbuffer, 1); +// return readbuffer[0]; +// //return status; +//} + + + +//uint8_t WHS_Fan_Read_Registers() +//{ +// uint8_t status = OK, i = 0; +// +// +// for(i=40;i<EMC2302_Size;i++) +// { +// writebuffer[0] = WHS_EMC2302_Reg_Add[i]; +// status |= I2C_Write(I2C_ID_WHS_CARD, I2C_WHS_FAN_SLAVE_ADD, writebuffer, 1); +// delayUs(10);//TODO - check the delay +// status |= I2C_Read(I2C_ID_WHS_CARD, I2C_WHS_FAN_SLAVE_ADD + 1, readbuffer, 1); +// EMC2302_Read.Buf[i] = readbuffer[0]; +// delayms(5);//TODO - check the delay +// } +// return status; +//} + + + +uint8_t D_Fan_config(uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr) + +{ + uint8_t status = OK; + + //EMC2302_Write.Reg.PWM_Polarity_Config = 0x0;//Bit0 invert PWM1, Bit2 invert PWM2 + //WHS_Fan_PWM_Polarity_Config(); + + //Output is configured as a push-pull output + EMC2302_Write.Reg.PWM_Output_Config = 0x3;//Bit0 Output PWM1, Bit2 Output PWM2, 0 open drain, 1 push-pull + D_Fan_PWM_Output_Config(EMC2302_I2C_bus_number ,EMC2302_I2C_addr); + +// //Max Freq. +// EMC2302_Write.Reg.PWM_Base_Freq = (FAN_FREQ_26KHZ << 2) | FAN_FREQ_26KHZ; +// WHS_Fan_PWM_Base_Frequency(); +// +// +// WHS_Read_Config_Reg(); +// if (EMC2302_Read.Reg.PWM_Output_Config != EMC2302_Write.Reg.PWM_Output_Config) +// status |= ERROR ; + + EMC2302_Write.Reg.Fan_Setting[0] = D_Fan_PWM_Command[0]; //Fan 1 Setting - 0xFF Full PWM 0x80 = 50% FF = 100% 0 - STOP + D_Fan_Setting( EMC2302_I2C_bus_number , EMC2302_I2C_addr, 0); + delayms(5);//TODO - check the delay + D_Fan_Read_Tacho( EMC2302_I2C_bus_number , EMC2302_I2C_addr, 0); + + EMC2302_Write.Reg.Fan_Setting[1] = D_Fan_PWM_Command[1]; //Fan 1 Setting - 0xFF Full PWM 0x80 = 50% FF = 100% 0 - STOP + D_Fan_Setting( EMC2302_I2C_bus_number , EMC2302_I2C_addr, 1); + delayms(5);//TODO - check the delay + D_Fan_Read_Tacho( EMC2302_I2C_bus_number , EMC2302_I2C_addr, 1); + + return status; +} + + +void Test_WHS_fan_Click(uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr) +{ + static uint8_t once = 1; + if (once) + { + #ifdef Test_WHSCard_With_DispCard_I2C4_Add0xE2_DispID_0 + Select_Main_WHS_Mux_Channel_test(); + #else + Select_Main_WHS_Mux_Channel(); + #endif + + //once = 0; + } + D_fan_click_productID(EMC2302_I2C_bus_number , EMC2302_I2C_addr); + D_fan_click_manufactuerID(EMC2302_I2C_bus_number , EMC2302_I2C_addr); + D_fan_click_revision(EMC2302_I2C_bus_number , EMC2302_I2C_addr); + D_Read_Config_Reg(EMC2302_I2C_bus_number , EMC2302_I2C_addr); + //WHS_Fan_Read_Registers(); + D_Fan_config( EMC2302_I2C_bus_number , EMC2302_I2C_addr); +} + +/* ***** use only the next func: ***/ +/* ***** use only the next func: ***/ +/* ***** use only the next func: ***/ +/* ***** use only the next func: ***/ + +uint8_t D_Fan_PWM_Output_Config(uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr) +{ + uint8_t status = ERROR; + + if(EMC2302_Write.Reg.PWM_Output_Config <=0x03)//Bit0 Output PWM1, Bit2 Output PWM2, 0 open drain, 1 push-pull + { + writebuffer[0] = EMC2301_PWM_OUTPUT_CONFIG; + writebuffer[1] = EMC2302_Write.Reg.PWM_Output_Config;; + status = I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 2); + + } + return status; +} + +uint8_t D_Fan_Setting(uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr, bool Fan) +{ + uint8_t status = ERROR; + + if(Fan == 0) + { + writebuffer[0] = EMC2301_FAN_1_SETTING; + writebuffer[1] = EMC2302_Write.Reg.Fan_Setting[0]; + } + else + { + writebuffer[0] = EMC2301_FAN_2_SETTING; + writebuffer[1] = EMC2302_Write.Reg.Fan_Setting[1]; + } + + status = I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 2); + + return status; +} + +uint8_t D_Fan_Read_Tacho(uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr, bool Fan) +{ + uint8_t status = ERROR; + + if(Fan == 0) + { + writebuffer[0] = EMC2301_TACH_1_READING_HIGH; + status = I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + EMC2302_Read.Reg.TACHReading_High[0] = readbuffer[0]; + + writebuffer[0] = EMC2301_TACH_1_READING_LOW; + status = I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + EMC2302_Read.Reg.TACHReading_Low[0] = readbuffer[0]; + + Fan_Tach[0] = (EMC2302_Read.Reg.TACHReading_High[0] << 8) | EMC2302_Read.Reg.TACHReading_Low[0]; + } + else + { + writebuffer[0] = EMC2301_TACH_2_READING_HIGH; + status = I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + EMC2302_Read.Reg.TACHReading_High[1] = readbuffer[0]; + + writebuffer[0] = EMC2301_TACH_2_READING_LOW; + status = I2C_Write(EMC2302_I2C_bus_number, EMC2302_I2C_addr, writebuffer, 1); + delayUs(10);//TODO - check the delay + status |= I2C_Read(EMC2302_I2C_bus_number, EMC2302_I2C_addr + 1, readbuffer, 1); + EMC2302_Read.Reg.TACHReading_Low[1] = readbuffer[0]; + + Fan_Tach[1] = (EMC2302_Read.Reg.TACHReading_High[1] << 8) | EMC2302_Read.Reg.TACHReading_Low[1]; + } + + return status; +} + + +uint8_t D_Fan_PWM_Control(uint8_t EMC2302_I2C_bus_number ,uint8_t EMC2302_I2C_addr, uint8_t Fan_ID, uint8_t PWM) +{ + uint8_t status = OK; + + // Select_Main_WHS_Mux_Channel(); + + if(Fan_ID < 0x02) + { + D_Fan_PWM_Command[Fan_ID] = PWM; + } + else + status |= ERROR; + + + EMC2302_Write.Reg.PWM_Output_Config |= (0x1 << Fan_ID);//Bit0 Output PWM1, Bit2 Output PWM2, 0 open drain, 1 push-pull + status |= D_Fan_PWM_Output_Config( EMC2302_I2C_bus_number , EMC2302_I2C_addr); + + EMC2302_Write.Reg.Fan_Setting[Fan_ID] = D_Fan_PWM_Command[Fan_ID]; //Fan 1 Setting - 0xFF Full PWM 0x80 = 50% FF = 100% 0 - STOP + status |= D_Fan_Setting( EMC2302_I2C_bus_number , EMC2302_I2C_addr, Fan_ID); + delayms(5);//TODO - check the delay + status |= D_Fan_Read_Tacho( EMC2302_I2C_bus_number , EMC2302_I2C_addr, Fan_ID); + + return status; +} + +/* +control by: +WHS_Fan_PWM_Control(0, 0xFF);//0-0xFF +WHS_Fan_PWM_Control(1, 0xFF);//0-0xFF +*/ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_EMC2302_fan.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_EMC2302_fan.h new file mode 100644 index 000000000..c4b0b6ba7 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_EMC2302_fan.h @@ -0,0 +1,811 @@ +/* + * Fan_Click.h + * + * Created on: Oct 27, 2019 + * Author: avi + */ + +#ifndef DRIVERS_I2C_COMMUNICATION_EMC2302_FAN_DRIVER_H_ +#define DRIVERS_I2C_COMMUNICATION_EMC2302_FAN_DRIVER_H_ + +#ifndef FAN_CLICK_H_ +#define FAN_CLICK_H_ + +/****************************************************************************** +* Includes +*******************************************************************************/ +#include <stdint.h> +#include <stdbool.h> + +/****************************************************************************** +* Preprocessor Constants +*******************************************************************************/ +#define EMC2301_I2C_ADDR 0x2F + +/** + * EMC2301 Registers + */ +#define EMC2301_CONFIGURATION 0x20 /**< Configures the clocking and watchdog functions. default 0x40 R/W */ +#define EMC2301_FAN_STATUS 0x24 /**< Stores the status bits for the RPM-based Fan Speed Control Algorithm. default 00 R-C */ +#define EMC2301_FAN_STALL_STATUS 0x25 /**< Stores status bits associated with a stalled fan. default 0x00 R-C */ +#define EMC2301_FAN_SPIN_STATUS 0x26 /**< Stores status bits associated with a spin-up failure. default 0x00 R-C */ +#define EMC2301_DRIVE_FAIL_STATUS 0x27 /**< Stores status bits associated with drive failure. default 0x00 R-C */ +#define EMC2301_FAN_INTERRUPT_ENABLE 0x29 /**< Controls the masking of interrupts on all channels. default 0x00 R/W */ +#define EMC2301_PWM_POLARITY 0x2A /**< Configures polarity of the PWM driver. default 0x00 R/W */ +#define EMC2301_PWM_OUTPUT_CONFIG 0x2B /**< Configures output type of the PWM driver. default 0x00 R/W */ +#define EMC2301_PWM_BASE_FREQ 0x2D /**< Selects the base frequency for the PWM output. default 0x00 R/W */ + +#define EMC2301_FAN_1_SETTING 0x30 /**< Always displays the most recent FAN_1 input setting for the FAN_1. If the RPM based FAN_1 speed + control algorithm is disabled, allows direct user control of the FAN_1 driver. default 0x00 R/W */ +#define EMC2301_PWM_1_DIVIDE 0x31 /**< Sores the divide ratio to set the freq of the FAN_1 driver. default 0x01 R/W */ +#define EMC2301_FAN_1_CONFIG1 0x32 /**< Sets configuration values for the RPM base FAN_1 speed control. default 0x2B R/W */ +#define EMC2301_FAN_1_CONFIG2 0x33 /**< Sets additional configuration values for the FAN_1 driver. default 0x28 R/W */ +#define EMC2301_GAIN_1 0x35 /**< Holds the gain terms used by the RPM based FAN_1 Speed Control Algorithm for the FAN_1 driver. 0x2A R/W */ +#define EMC2301_FAN_1_SPINUP 0x36 /**< Sets the configuration values for Spin Up Routine of the FAN_1 driver. default 0x19 R/W */ +#define EMC2301_FAN_1_MAX_STEP 0x37 /**< Sets the maximum change per update for the FAN_1 drive. default 0x10 R/W */ +#define EMC2301_FAN_1_MIN_DRIVE 0x38 /**< Sets the min drive value of the FAN_1 driver. default 0x66 40% R/W */ +#define EMC2301_FAN_1_VALID_TACH 0x39 /**< Holds the tachometer reading that indicates FAN_1 is spinning properly. default 0xF5 R/W */ +#define EMC2301_FAN_1_FAIL_LOW 0x3A /**< Stores the number of tach counts used to determine how the actual FAN_1 speed must match the target FAN_1 speed at full scale. */ +#define EMC2301_FAN_1_FAIL_HIGH 0x3B +#define EMC2301_TACH_1_TARGET_LOW 0x3C /**< Holds the target tachometer reading low byte for the FAN_1. default 0xF8 R/W */ +#define EMC2301_TACH_1_TARGET_HIGH 0x3D /**< Holds the target tachometer reading high byte for the FAN_1. default 0xFF R/W */ +#define EMC2301_TACH_1_READING_HIGH 0x3E /**< Holds the tachometer reading high byte for the FAN_1. default 0xFF R/W */ +#define EMC2301_TACH_1_READING_LOW 0x3F /**< Holds the tachometer reading low byte for the FAN_1. default 0xF8 R/W */ + +#define EMC2301_FAN_2_SETTING 0x40 /**< Always displays the most recent FAN_1 input setting for the FAN_1. If the RPM based FAN_1 speed + control algorithm is disabled, allows direct user control of the FAN_1 driver. default 0x00 R/W */ +#define EMC2301_PWM_2_DIVIDE 0x41 /**< Sores the divide ratio to set the freq of the FAN_1 driver. default 0x01 R/W */ +#define EMC2301_FAN_2_CONFIG1 0x42 /**< Sets configuration values for the RPM base FAN_1 speed control. default 0x2B R/W */ +#define EMC2301_FAN_2_CONFIG2 0x43 /**< Sets additional configuration values for the FAN_1 driver. default 0x28 R/W */ +#define EMC2301_GAIN_2 0x45 /**< Holds the gain terms used by the RPM based FAN_1 Speed Control Algorithm for the FAN_1 driver. 0x2A R/W */ +#define EMC2301_FAN_2_SPINUP 0x46 /**< Sets the configuration values for Spin Up Routine of the FAN_1 driver. default 0x19 R/W */ +#define EMC2301_FAN_2_MAX_STEP 0x47 /**< Sets the maximum change per update for the FAN_1 drive. default 0x10 R/W */ +#define EMC2301_FAN_2_MIN_DRIVE 0x48 /**< Sets the min drive value of the FAN_1 driver. default 0x66 40% R/W */ +#define EMC2301_FAN_2_VALID_TACH 0x49 /**< Holds the tachometer reading that indicates FAN_1 is spinning properly. default 0xF5 R/W */ +#define EMC2301_FAN_2_FAIL_LOW 0x4A /**< Stores the number of tach counts used to determine how the actual FAN_1 speed must match the target FAN_1 speed at full scale. */ +#define EMC2301_FAN_2_FAIL_HIGH 0x4B +#define EMC2301_TACH_2_TARGET_LOW 0x4C /**< Holds the target tachometer reading low byte for the FAN_1. default 0xF8 R/W */ +#define EMC2301_TACH_2_TARGET_HIGH 0x4D /**< Holds the target tachometer reading high byte for the FAN_1. default 0xFF R/W */ +#define EMC2301_TACH_2_READING_HIGH 0x4E /**< Holds the tachometer reading high byte for the FAN_1. default 0xFF R/W */ +#define EMC2301_TACH_2_READING_LOW 0x4F /**< Holds the tachometer reading low byte for the FAN_1. default 0xF8 R/W */ + +#define EMC2301_SOFTWARE_LOCK 0xEF /**< Locks all SWL registers. default 0x00 R/W */ +#define EMC2301_PRODUCT_ID 0xFD /**< Stores the unique product ID. default 0x37 R */ +#define EMC2301_MANUFACTUERE_ID 0xFE /**< Stores the manufacturer ID. default 0x5D R */ +#define EMC2301_REVISION 0xFF /**< Revision. default 0x80 R */ + +/****************************************************************************** +* Configuration Constants +*******************************************************************************/ + +/****************************************************************************** +* Macros +*******************************************************************************/ + +/****************************************************************************** +* Typedefs +*******************************************************************************/ +/** + * @enum Configuration Bits + */ +enum +{ + USE_EXT_CLK = 0, /**< Enables the EMC2301 to use a clock present on the CLK */ + DR_EXT_CLK = 2, /**< Enables the internal tach clock */ + WD_EN = 32, /**< Enables the watchdog timer. default 0 */ + DIS_TO = 64, /**< Disables the SMBus timeout function, 1 default */ + MASK = 128 /**< Blocks the ALERT pin from being asserted, 0 default */ +}; + +/** + * @enum Status register results + */ +typedef enum +{ + FAN_STALL = 1, /**< Indicates that the fan driver has stalled */ + FAN_SPIN = 2, /**< Indicates that the fan driver cannot spin up */ + FAN_DRIVE_FAIL = 4, /**< Indicates that the driver cannot meet the programmed fan speed */ + FAN_WATCH = 128 /**< Indicates that the watchdog timer has expired */ +} fan_status_t; + +/** + * @enum FAN PWM Base frequencies + */ +typedef enum +{ + FAN_FREQ_26KHZ = 0, /**< Base of 26kHz */ + FAN_FREQ_19_531KHZ, /**< Base of 19.5431kHz */ + FAN_FREQ_4_882HZ, /**< Base of 4.882Hz */ + FAN_FREQ_2_441HZ /**< Base of 2.441Hz */ +} fan_base_freq_t; + + +/** + * @enum Range of tach readings + * + * Adjusts the range of reported and programmed tachometer reading values. + * The RANGE bits determine the weighting of all TACH values + */ +typedef enum +{ + RPM_MIN_500, + RPM_MIN_1000, + RPM_MIN_2000, + RPM_MIN_4000 +} fan_range_t; + +/** + * @enum Number of Fan Edges + * + * Determines the minimum number of edges that must be detected on the + * TACHx signal to determine a single rotation. A typical fan measured 5 edges + * ( for a 2-pole fan ). For more accurate tachometer measurement, the minimum + * number of edges measured may be increased. + */ +typedef enum +{ + EDGE_1_POLE, + EDGE_2_POLE, + EDGE_3_POLE, + EDGE_4_POLE +} fan_edges_t; + +/** + * @enum Update Time Configuration + */ +typedef enum +{ + UPDATE_100MS, + UPDATE_200MS, + UPDATE_300MS, + UPDATE_400MS, + UPDATE_500MS, + UPDATE_800MS, + UPDATE_1200MS, + UPDATE_1600MS +} fan_update_t; + +/** + * @enum Derivative options + * + * Control some of the advanced options that affect the derivative portion of + * the RPM-based Fan Speed Control Algorithm + */ +typedef enum +{ + DERIVATIVE_NONE, + DERIVATIVE_BASIC, + DERIVATIVE_STEP, + DERIVATIVE_BOTH +} fan_derivative_t; + + +/** + * @enum Error range options + * + * Control some of the advanced options that affect the error window. When the + * measured fan speed is within the programmed error window around the target + * speed, then the fan drive setting is not updated. The algorithm will + * continue to monitor the fan speed and calculate necessary drive setting + * changes based on the error. + */ +typedef enum +{ + RPM_0, + RPM_50, + RPM_100, + RPM_200 +} fan_error_t; + + +/** + * @enum Gain for PID settings + * + */ +typedef enum +{ + FAN_GAIN1X, + FAN_GAIN2X, + FAN_GAIN4X, + FAN_GAIN8X +} fan_gain_t; + + +/** + * @enum How mnay update cycles are used for detection of error + * + * Determines how many update cycles are used for the Drive Fail detection + * function +*/ +typedef enum +{ + DRIVE_CNT_DISABLED, + DRIVE_CNT_16, + DRIVE_CNT_32, + DRIVE_CNT_64, +} fan_drive_fail_count_t; + + +/** + * @enum Spin up percent + * + * Determines the final drive level that is used by the Spin Up Routine + */ +typedef enum +{ + SPINUP_30PERCENT, /**< 30% of duty */ + SPINUP_35PERCENT, /**< 35% of duty */ + SPINUP_40PERCENT, /**< 40% of duty */ + SPINUP_45PERCENT, /**< 45% of duty */ + SPINUP_50PERCENT, /**< 50% of duty */ + SPINUP_55PERCENT, /**< 55% of duty */ + SPINUP_60PERCENT, /**< 60% of duty */ + SPINUP_65PERCENT /**< 65% of duty */ +} fan_spinup_t; + + +/** + * @enum Spin time options + * + */ +typedef enum +{ + SPINUP_250MS, /**< 250ms delay */ + SPINUP_500, /**< 500ms delay */ + SPINUP_1S, /**< 1s delay */ + SPINUP_2S /**< 2s delay */ +} fan_spintime_t; + +/****************************************************************************** +* Variables +*******************************************************************************/ + + +/****************************************************************************** +* Function Prototypes +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initializes the emc2301 + * + * @param address - slave address of the controller + * @return int - 0 success / -1 error + * + * @code + * if( !fan_click_init( EMC2301_I2C_ADDRESS ) ) + * return ERROR_INIT; + * @endcode + */ +int fan_click_init( uint8_t address ); + +/** + * @brief Specifies external clock speed if different from standard + * + * @note Only used if external clock differs from standard(rare). Changes tach + * calculations - use caution. + * + * @param freq - frequency of clock + */ +void fan_click_ext_clock( double freq ); + +/** + * @brief Fan configuration + * + * The Configuration Register controls the basic functionality of the EMC2301. + * + * @param config + * + * @code + * fan_click_config( USE_EXT_CLK | MASK ); + * @endcode + */ +void fan_click_config( uint8_t config ); + +/** + * @brief Fan status + * + * The Fan Status register indicates that the fan driver has stalled or failed + * or that the Watchdog Timer has expired. + * + * @return + * @retval FAN_STALL = 1 + * @retval FAN_SPIN = 2 + * @retval FAN_DRIVE_FAIL = 4 + * @retval FAN_WATCH = 128 + */ +fan_status_t fan_click_get_status( void ); + +/** + * @brief Fan stall status + * + * The Fan Stall Status register indicates that the fan driver has detected a + * stalled condition + * + * @return + * @retval FAN_STALL = 1 + */ +fan_status_t fan_click_get_stall_status( void ); + +/** + * @brief Fan spin status + * + * The Fan Spin Status register indicates that the fan driver has failed to + * spin-up. + * + * @return + * @retval 1 FAN_SPIN has failed + * @retval 0 FAN OK + */ +uint8_t fan_click_get_spin_status( void ); + +/** + * @brief Fan click drive fail status + * + * The Fan Drive Fail Status register indicates that the fan driver cannot + * drive to the programmed speed even at 100% duty cycle. + * + * @return + * @retval 1 DRIVE_FAIL + * @retval 0 DRIVE OK + */ +uint8_t fan_click_get_drive_fail( void ); + +/** + * @brief Enable or disable external interrupts + * + * The Fan Interrupt Enable controls the masking for the Fan channel. When a + * channel is enabled, it will cause the ALERT# pin to be asserted when an + * error condition is detected. + * + */ +void fan_click_interrupts( bool enable ); + +/** + * @brief Reverse polarity of fan. + * + * Determines the polarity of the PWM. + * + * @param inverted - false default, true inverted + */ +void fan_click_polarity( bool inverted ); + +/** + * @brief Configure PWM type + * + * Determines the output type of the PWM driver. + * + * @param push_pull - false open drain / true push-pull + * @note + * Default mode is open drain + */ +void fan_click_pwm_config( bool push_pull ); + +/** + * @brief Base frequency + * + * The PWM Base Frequency register determines the base frequency that is used + * with the PWM Divide register to determine the final PWM frequency. + * + * @param freq + */ +//void fan_click_pwm_base( fan_base_freq_t freq ); + +/** + * @brief Fan setting + * + * The Fan Setting register always displays the current setting of the fan + * driver. Reading from the register will report the current fan speed setting + * of the fan driver regardless of the operating mode. Therefore it is + * possible that reading from this register will not report data that was + * previously written into this register. + * + * @param percentage - percentage of duty + * + * @note While the RPM-based Fan Speed Control Algorithm is active, the + * register is read only. Writing to the register will have no effect and the + * data will not be stored. + * + */ +void fan_click_settings( double percentage ); + +/** + * @brief Read basic setting + * + * The Fan Setting register always displays the current setting of the fan + * driver. Reading from the register will report the current fan speed setting + * of the fan driver regardless of the operating mode. Therefore it is + * possible that reading from this register will not report data that was + * previously written into this register. + * + * @param settings + * + * @return double - percentage of current drive settings. + * + * @note While the RPM-based Fan Speed Control Algorithm is active, the + * register is read only. Writing to the register will have no effect and the + * data will not be stored. + */ +double fan_click_get_settings( void ); + +/** + * @brief Divide PWM signal + * + * The PWM Divide registers determine the final frequency of the PWM Fan + * Driver. The driver base frequency is divided by the value of the PWM Divide + * Register to determine the final frequency. The duty cycle settings are not + * affected by these settings, only the final frequency of the PWM driver. A + * value of 00h will be decoded as 01h. + * + * @param divide + */ +void fan_click_set_PWM_divide( uint8_t divide ); + +/** + * @brief Enable Fan Control Algorithm + * + * Changes the mode from manual to automatic fan speed control. + * + * false - (default) the control circuitry is disabled and the fan driver + * output is determined by the Fan Driver Setting Register. + * true - the control circuitry is enabled and the Fan Driver output will be + * automatically updated to maintain the programmed fan speed as indicated by + * the TACH Target Register. + * + * @param fsc - true enables fan control, false manual mode + */ +void fan_click_config_enableFSC( bool fsc ); + +/** + * @brief Number of edges that needs to be detected + * + * Adjusts the range of reported and programmed tachometer reading values. + * The RANGE bits determine the weighting of all TACH values + * + * @param range + */ +void fan_click_config_range( fan_range_t range ); + +/** + * @brief Number of edges on fan + * + * Determines the minimum number of edges that must be detected on the TACHx + * signal to determine a single rotation. A typical fan measured 5 edges + * (for a 2-pole fan). For more accurate tachometer measurement, the minimum + * number of edges measured may be increased. + * + * @param edges + */ +void fan_click_config_edges( fan_edges_t edges ); + +/** + * @brief Update time + * + * determines the base time between fan driver updates. The Update Time, along + * with the Fan Step Register, is used to control the ramp rate of the drive + * response to provide a cleaner transition of the actual fan operation as + * the desired fan speed changes. + * + * @param update + */ +void fan_click_config_update( fan_update_t update ); + +/** + * @brief Ramp up mode + * + * Enables ramp rate control when the fan driver is operated in the Direct + * Setting Mode + * + * false (default) - Ramp rate control is disabled. When the fan driver is + * operating in Direct Setting mode, the fan setting will instantly transition + * to the next programmed setting. + * + * true - Ramp rate control is enabled. When the fan driver is operating in + * Direct Setting mode, the fan drive setting will follow the ramp rate + * controls as determined by the Fan Step and Update Time settings. The + * maximum fan drive setting step is capped at the Fan Step setting and is + * updated based on the Update Time. + * + * @param rampControl + */ +void fan_click_config_enableRamp( bool rampControl ); + +/** + * @brief Glitch enable + * + * Disables the low pass glitch filter that removes high frequency noise + * injected on the TACHx pin. + * + * @param glitch + */ +void fan_click_config_enableGlitch( bool glitch ); + +/** + * @brief Derivative + * + * Control some of the advanced options that affect the derivative portion of + * the RPM-based Fan Speed Control Algorithm + * + * @param derivative - Basic derivative / Step Derivative / Both + * + * @note BASIC is default + */ +void fan_click_config_derivative( fan_derivative_t derivative ); + +/** + * @brief Error Range + * + * Control some of the advanced options that affect the error window. When the + * measured fan speed is within the programmed error window around the target + * speed, then the fan drive setting is not updated. + * + * @param error + */ +void fan_click_config_errorRange( fan_error_t error ); + +/** + * @brief Gain D + * + * Control some of the advanced options that affect the derivative portion of + * the RPM-based Fan Speed Control Algorithm. The Gain register stores the + * gain terms used by the proportional and integral portions of the RPM-based + * Fan Speed Control Algorithm. These gain terms are used as the KD, KI, and + * KP gain terms in a classic PID control solution. + * + * @param gain + */ +void fan_click_config_gaind( fan_gain_t gain ); + +/** + * @brief Gain I + * + * Control some of the advanced options that affect the derivative portion of + * the RPM-based Fan Speed Control Algorithm. The Gain register stores the + * gain terms used by the proportional and integral portions of the RPM-based + * Fan Speed Control Algorithm. These gain terms are used as the KD, KI, and + * KP gain terms in a classic PID control solution. + * + * @param gain + */ +void fan_click_config_gaini( fan_gain_t gain ); + +/** + * @brief Gain P + * + * Control some of the advanced options that affect the derivative portion of + * the RPM-based Fan Speed Control Algorithm. The Gain register stores the + * gain terms used by the proportional and integral portions of the RPM-based + * Fan Speed Control Algorithm. These gain terms are used as the KD, KI, and + * KP gain terms in a classic PID control solution. + * + * @param gain + */ +void fan_click_config_gainp( fan_gain_t gain ); + +/** + * @brief Drive Fail Count + * + * Determines how many update cycles are used for the Drive Fail + * detection function. + * + * @param count - Disabled / 16 / 32 / 64 + */ +void fan_click_config_drivefail( fan_drive_fail_count_t count ); + +/** + * @brief fan_click_config_enableNoKick + * + * Determines if the Spin Up Routine will drive the fan to 100% duty cycle for + * 1/4 of the programmed spin up time before driving it at the programmed + * level. + * + * @param noKick + * false = The spin up routine will drive the fan to 100% for + * 1/4 of the programmed spin up time before reverting to the programmed spin + * level. + * true = The spin up routine will not drive the fan driver to 100%. It will + * set the drive at the programmed spin level for the entire duration of the + * programmed spin up time. + */ +void fan_click_config_enableNoKick( bool noKick ); + +/** + * @brief fan_click_config_spinLevel + * + * Determines if the Spin Up Routine will drive the fan to 100% duty cycle for + * 1/4 of the programmed spin up time before driving it at the programmed + * level. + * + * @param spin + * + * @code + * fan_click_config_spinLevel( SPINUP_60PERCENT ); + */ +void fan_click_config_spinLevel( fan_spinup_t spin ); + +/** + * @brief fan_click_config_spinTime + * + * The Fan Spin Up Configuration register controls the settings of Spin Up + * Routine. + * + * @param time + * + * @note The Fan Spin Up Configuration register is software locked. + */ +void fan_click_config_spinTime( fan_spintime_t time ); + +/** + * @brief fan_click_set_max_step + * + * The Fan Max Step register, along with the Update Time, controls the ramp + * rate of the fan driver response calculated by the RPM-based Fan Speed + * Control Algorithm. The value of the register represents the maximum step + * size the fan driver will take between update times + * + * @param step + * + * @note When the FSC algorithm is enabled, Ramp Rate control is automatically + * used. + */ +void fan_click_set_max_step( uint8_t step ); + +/** + * @brief fan_click_set_min_drive + * + * The Fan Minimum Drive register stores the minimum drive setting for the + * RPM-based Fan Speed Control Algorithm. The RPM-based Fan Speed Control + * Algorithm will not drive the fan at a level lower than the minimum drive + * unless the target Fan Speed is set at FFh + * + * @param drive + */ +void fan_click_set_min_drive( double min_drive ); + + +/*************************************** + ********** Tach Functions ************* + **************************************/ +/** + * @brief fan_click_set_valid_tach + * + * The Valid TACH Count register stores the maximum TACH Reading Register + * value to indicate that the fan is spinning properly. The value is + * referenced at the end of the Spin Up Routine to determine if the fan has + * started operating and decide if the device needs to retry. + * + * @param tach + * + * @note The Valid TACH Count register is software locked. + */ +void fan_click_set_valid_tach( uint16_t tach ); + +/** + * @brief fan_click_set_valid_tach + * + * The Valid TACH Count register stores the maximum TACH Reading Register + * value to indicate that the fan is spinning properly. The value is + * referenced at the end of the Spin Up Routine to determine if the fan has + * started operating and decide if the device needs to retry. + * + * @return uint16_t + * + * @note The Valid TACH Count register is software locked. + */ +uint16_t fan_click_get_valid_tach( void ); + +/** + * @brief fan_click_get_driveband_fail + * + * The Fan Drive Fail Band Registers store the number of tach counts used by + * the Fan Drive Fail detection circuitry. This circuitry is activated when + * the fan drive setting high byte is at FFh. When it is enabled, the actual + * measured fan speed is compared against the target fan speed. These + * registers are only used when the FSC is active. + * + * @return + */ +uint16_t fan_click_get_driveband_fail( void ); + +/** + * @brief fan_click_set_target_tach + * + * The TACH Target Registers hold the target tachometer value that is + * maintained by the RPM-based Fan Speed Control Algorithm. + * + * The value in the TACH Target Registers will always reflect the current + * TACH Target value. + * + * If the algorithm is enabled, setting the TACH Target + * Register to FFh will disable the fan driver (set the fan drive setting to + * 0%). Setting the TACH Target to any other value (from a setting of FFh) + * will cause the algorithm to invoke the Spin Up Routine after which it will + * function normally. + * + * The Tach Target is not applied until the high byte is written. Once the + * high byte is written, the current value of both high and low bytes will be + * used as the next Tach target. + * + * + * @param tach - RPM 12000 + */ +void fan_click_set_target_tach( uint16_t tach ); + + +/** + * @brief fan_click_get_tach + * + * The Valid TACH Count register stores the maximum TACH Reading Register + * value to indicate that the fan is spinning properly. The value is + * referenced at the end of the Spin Up Routine to determine if the fan has + * started operating and decide if the device needs to retry. + * + * @note The Valid TACH Count register is software locked. If the TACH Reading + * Register value exceeds the Valid TACH Count Register (indicating that the + * Fan RPM is below the threshold set by this count), then a stalled fan is + * detected. In this condition, the algorithm will automatically begin its + * Spin Up Routine. + * + * @return uint16_t + * + */ +uint16_t fan_click_get_tach( void ); + + +/**************************************** + ******* Informational Functions ******** + ***************************************/ +/** + * @brief fan_click_lock_registers + * + * The Lock Column describes the locking mechanism, if any, used for + * individual registers. All SWL registers are Software Locked and therefore + * made read-only when the LOCK bit is set. + * + */ +void fan_click_lock_registers( bool lock ); + +/** + * @brief fan_click_productID + * + * The Product ID Register contains a unique 8-bit word that identifies the + * product. + * + * @return Product ID + */ +uint8_t fan_click_productID( void ); + +/** + * @brief fan_click_manufactuerID + * + * The Manufacturer ID Register contains an 8-bit word that identifies SMSC. + * + * @return Manufacturer ID + */ +uint8_t fan_click_manufactuerID( void ); + + +/** + * @brief fan_click_revision + * + * The Revision Register contains an 8-bit word that identifies the die + * revision. + * + * @return Revision number + */ +uint8_t fan_click_revision( void ); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /*FILE_CLICK_H_*/ + + +/*** End of File **************************************************************/ + + + +#endif /* DRIVERS_I2C_COMMUNICATION_EMC2302_FAN_DRIVER_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_Fan.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_Fan.c new file mode 100644 index 000000000..c18dc3be3 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_Fan.c @@ -0,0 +1,23 @@ +/* + * Head_Fan.c + * + * Created on: Jul 2, 2019 + * Author: avi + */ +#include "include.h" + +/* + + EMC2301 / EMC2302 + +https://github.com/MicrochipTech/gcp-iot-core-examples/blob/master/src/devices/fan_click.c +https://github.com/MikroElektronika/HEXIWEAR/blob/master/SW/Click%20Examples%20mikroC/examples/iqRF/fan_click.h + +https://github.com/TekkaTim/esp32_learning/blob/master/lib/EMC2302.py + +*/ + +//FAN EMC2302-1-AIZL + + + diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_Fan.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_Fan.h new file mode 100644 index 000000000..5956e3d08 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_EMC2302_Fan/D_Fan.h @@ -0,0 +1,75 @@ +/* + * Head_Fan.h + * + * Created on: Jul 2, 2019 + * Author: avi + */ + +#ifndef DRIVERS_I2C_COMMUNICATION_HEAD_CARD_FAN_HEAD_FAN_H_ +#define DRIVERS_I2C_COMMUNICATION_HEAD_CARD_FAN_HEAD_FAN_H_ + +typedef struct +{ + //Configuration and control + uint8_t Configuration ; + uint8_t Fan_Status ; + uint8_t Fan_Stall_Status ; + uint8_t Fan_Spin_Status ; + uint8_t Drive_Fail_Status ; + uint8_t Fan_Interrupt_Enable ; + uint8_t PWM_Polarity_Config ; + uint8_t PWM_Output_Config ; + uint8_t PWM_Base_Freq ; + //Fan 1 & 2 Control Registers + uint8_t Fan_Setting[2] ; + uint8_t PWM_Divide[2] ; + uint8_t FanConfig_1[2] ; + uint8_t FanConfig_2[2] ; + uint8_t Gain[2] ; + uint8_t FanSpin_Up_Config[2] ; + uint8_t FanMax_Step[2] ; + uint8_t FanMinimum_Drive[2] ; + uint8_t FanValid_TACH_Count[2] ; + uint8_t FanDrive_Fail_Low[2] ; + uint8_t FanDrive_Fail_High[2] ; + uint8_t TACHTarget_Low[2] ; + uint8_t TACHTarget_High[2] ; + uint16_t TACHReading_High[2] ; + uint8_t TACHReading_Low[2] ; + //Lock Register + uint8_t Software_Lock ; + //Revision Registers + uint8_t Product_ID ; + uint8_t Manufacturer_ID ; + uint8_t Revision ; +}EMC2302_Register; + +#define EMC2302_Size sizeof(EMC2302_Register)//43 + +typedef struct +{ + uint8_t Product_ID; + uint8_t Manufactuere_ID; + uint8_t Revision; +}FAN_CLICK_INFO; + +typedef union +{ + EMC2302_Register Reg; + uint8_t Buf[EMC2302_Size]; +}EMC2302_READ; + +typedef union +{ + EMC2302_Register Reg; + uint8_t Buf[EMC2302_Size]; +}EMC2302_WRITE; + +void Test_fan_Click(); + +extern FAN_CLICK_INFO Fan_Click_Info; +extern EMC2302_READ EMC2302_Read; + +uint8_t Head_Fan_PWM_Control(uint8_t Fan_ID, uint8_t PWM); + +#endif /* DRIVERS_I2C_COMMUNICATION_HEAD_CARD_FAN_HEAD_FAN_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.c new file mode 100644 index 000000000..f6fd8e9cd --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.c @@ -0,0 +1,62 @@ +/* + * TCA9546_Driver.c + * + * Created on: 11 11, 2019 + * Author: Shai + */ + +#include "include.h" +#include <DataDef.h> +#include <Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.h> +#include "drivers/I2C_Communication/I2C.h" + + +bool D_TCA9546_Reset_n(bool reset) +{ + bool ret = 0; + return ret; +} + +bool D_TCA9546_Select_Channel(uint8_t TCA9546A_I2C_bus_number ,uint8_t TCA9546A_I2C_addr ,TCA9546A_chnl_status chnl_status, TCA9546A_chnl chnl_number) +{ + bool status= OK; + + uint8_t Write_Buf[1]; + uint8_t Read_buf[1]; +#warning do we need to do write and read ??? + status |= I2C_Write(TCA9546A_I2C_bus_number, TCA9546A_I2C_addr, Write_Buf, 1); //status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2); + delayUs(10);//TODO - check the delay + status = I2C_Read(TCA9546A_I2C_bus_number, TCA9546A_I2C_addr+1, Read_buf, 1 ); + if (chnl_status) + { + Write_Buf[0] = (Read_buf[1] | chnl_number); + } + else + { + Write_Buf[0] = ~(~Read_buf[1] | chnl_number); + } + + status |= I2C_Write(TCA9546A_I2C_bus_number, TCA9546A_I2C_addr, Write_Buf, 1); + + return status; +} + +bool D_TCA9546_Read_Channel(uint32_t TCA9546A_I2C_bus_number, uint32_t TCA9546A_I2C_addr, TCA9546A_chnl chnl_number, TCA9546A_chnl_status *chnl_stats) +{ + bool status= OK; + uint8_t Read_buf[1]; + + status = I2C_Read(TCA9546A_I2C_bus_number, TCA9546A_I2C_addr, Read_buf, 1 ); + if (Read_buf[1] & chnl_number ) + { + *chnl_stats = TCA9546A_chnl_OPEN; + } + else + { + *chnl_stats = TCA9546A_chnl_CLOSE; + } + + + return status; +} + diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.h new file mode 100644 index 000000000..f8db095fa --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.h @@ -0,0 +1,57 @@ +/* + * I2C_Head_Mux.h + * + * Created on: Jul 2, 2019 + * Author: avi + */ + +#ifndef TCA9546_DRIVERS_I2C_MUX_4chnl_H_ +#define TCA9546_DRIVERS_I2C_MUX_4chnl_H_ + +/* + * Standard-Mode (100kHz) and Fast-Mode (400 kHz) operation + * + * + * */ + + + +//I2C SLAVE ADDRESS 8 BIT !! + +#define TCA9546_reset 0 +/* +#define TCA9546A_chnl0 0x01 +#define TCA9546A_chnl1 0x02 +#define TCA9546A_chnl2 0x04 +#define TCA9546A_chnl3 0x08 +#define TCA9546A_All_chnl_OPEN 0xff +#define TCA9546A_All_chnl_CLOSE 0x00 +#define TCA9546A_chnl_OPEN 1 +#define TCA9546A_chnl_CLOSE 0 + +*/ + +typedef enum +{ + TCA9546A_All_chnl_CLOSE = 0, + TCA9546A_chnl0 = 1, + TCA9546A_chnl1 = 2, + TCA9546A_chnl2 = 4, + TCA9546A_chnl3 = 8, + TCA9546A_All_chnl_OPEN = 0xff +} TCA9546A_chnl; + +typedef enum +{ + TCA9546A_chnl_CLOSE = 0, + TCA9546A_chnl_OPEN +} TCA9546A_chnl_status; + +bool D_TCA9546_Reset_n(bool reset); + +bool D_TCA9546_Select_Channel(uint8_t TCA9546A_I2C_bus_number ,uint8_t TCA9546A_I2C_addr ,TCA9546A_chnl_status chnl_stats, TCA9546A_chnl chnl_number); +bool D_TCA9546_Read_Channel(uint32_t TCA9546A_I2C_bus_number, uint32_t TCA9546A_I2C_addr, TCA9546A_chnl chnl_number, TCA9546A_chnl_status *chnl_stats); + + + +#endif /* TCA9546_DRIVERS_I2C_MUX_4chnl_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Fan_Mux.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Fan_Mux.c new file mode 100644 index 000000000..257b124bb --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Fan_Mux.c @@ -0,0 +1,35 @@ +/* + * I2C_Head_Mux.c + * + * Created on: Jul 2, 2019 + * Author: avi + */ + +#include "include.h" +#include <DataDef.h> + +#include "drivers/I2C_Communication/I2C.h" + +#include "Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h" +#include "Drivers/I2C_Communication/WHS_Card/I2C_WHS_Fan_Mux.h" +#include "Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.h" + +uint32_t Select_Fan_Mux_Channel(TCA9546A_chnl Channel) +{ + uint32_t status= OK; + + uint8_t Write_Buf[1]; + + Select_Main_WHS_Mux_Channel(); + + Write_Buf[0] = Channel; //<< 4;//Channel 4 + + status = I2C_Write(I2C_ID_WHS_CARD, Fan_MUX_TCA9546A_0xE8, Write_Buf, 1); + + return status; +} + + + + + diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Fan_Mux.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Fan_Mux.h new file mode 100644 index 000000000..4c29e4ea8 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Fan_Mux.h @@ -0,0 +1,32 @@ +/* + * I2C_Head_Mux.h + * + * Created on: Jul 2, 2019 + * Author: avi + */ + +#ifndef DRIVERS_I2C_COMMUNICATION_WHS_CARD_I2C_WHS_FAN_MUX_H_ +#define DRIVERS_I2C_COMMUNICATION_WHS_CARD_I2C_WHS_FAN_MUX_H_ + +/* + * Standard-Mode (100kHz) and Fast-Mode (400 kHz) operation + * + * + * */ + +#include "Drivers/I2C_Communication/WHS_Card/D_TCA9546/TCA9546_Driver.h" + +uint32_t Reset_n(bool reset); + + +uint32_t Select_Fan_Mux_Channel(TCA9546A_chnl Channel); + +//uint32_t Select_Main_WHS_Mux_Channel(bool chnl_stats, uint32_t chnl_number); + + + +#define I2C_ID_WHS_CARD 0x03 +#define I2C3_MAIN_MUX_TCA9548A_0xE0 0xE0 //WHS - SD1, SC1 +#define Fan_MUX_TCA9546A_0xE8 0xE8 + +#endif /* DRIVERS_I2C_COMMUNICATION_WHS_CARD_I2C_WHS_FAN_MUX_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.c index c6e6297e1..c5ac1d8a8 100644 --- a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.c +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.c @@ -1,16 +1,50 @@ /* * I2C_WHS_Mux.c * - * Created on: Nov 10, 2019 + * Created on: Jul 2, 2019 * Author: avi */ - #include "include.h" #include <DataDef.h> -#include "I2C_WHS_Mux.h" +#include <Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h> #include "drivers/I2C_Communication/I2C.h" +#include <Drivers/I2C_Communication/Head_Card/I2C_Head_Mux.h> +/* +uint32_t Select_Main_WHS_Mux_Channel(bool chnl_stats, uint32_t chnl_number) +{ + uint32_t status= OK; + + static uint8_t Write_Buf; + + if (chnl_stats == TCA9548A_chnl_OPEN) // + { + Write_Buf = chnl_number; + } + else + { + Write_Buf = TCA9548A_All_chnl_CLOSE; + } + //Write_Buf[0] = 0x01 << 1;//Channel 1 + +// avi status = I2C_Write(I2C_ID_HEAD_CARD, I2C1_MAIN_MUX_TCA9548A_0xE0, &Write_Buf, 1); + + return status; +} + +uint32_t Select_Main_WHS_Mux_Channel_test() +{ + uint32_t status= OK; + + uint8_t Write_Buf[1]; + + Write_Buf[0] = 0x01 << 0;//Channel 0 + +//avi status = I2C_Write(I2C_ID_HEAD_CARD, I2C1_MAIN_MUX_TCA9548A_0xE0, Write_Buf, 1); + return status; +} +*/ #include "Drivers/I2C_Communication/Head_Card/I2C_Head_Mux.h" uint32_t Select_Main_WHS_Mux_Channel() @@ -23,7 +57,7 @@ uint32_t Select_Main_WHS_Mux_Channel() Write_Buf[0] = 0x01 << 1;//Channel 1 - status = I2C_Write(I2C_ID_WHS_CARD, I2C3_MAIN_MUX_TCA9548A_0xE0, Write_Buf, 1); + status = I2C_Write(I2C_ID_WHS_CARD, I2C2_MAIN_MUX_TCA9548A_0xE0, Write_Buf, 1); return status; } @@ -36,10 +70,7 @@ uint32_t Block_Main_WHS_Mux_Channel() Write_Buf[0] = 0x00;//Block all - status = I2C_Write(I2C_ID_WHS_CARD, I2C3_MAIN_MUX_TCA9548A_0xE0, Write_Buf, 1); + status = I2C_Write(I2C_ID_WHS_CARD, I2C2_MAIN_MUX_TCA9548A_0xE0, Write_Buf, 1); return status; } - - - diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h index 1e1331268..a949a0ea3 100644 --- a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h @@ -1,17 +1,43 @@ /* - * I2C_WHS_Mux.h + * I2C_Head_Mux.h * - * Created on: Nov 10, 2019 + * Created on: Jul 2, 2019 * Author: avi */ #ifndef DRIVERS_I2C_COMMUNICATION_WHS_CARD_I2C_WHS_MUX_H_ #define DRIVERS_I2C_COMMUNICATION_WHS_CARD_I2C_WHS_MUX_H_ -#define I2C_ID_WHS_CARD 0x03 -#define I2C3_MAIN_MUX_TCA9548A_0xE0 0xE0 //WHS - SD1, SC1 +/* + * Standard-Mode (100kHz) and Fast-Mode (400 kHz) operation + * + * + * */ + + + +//I2C SLAVE ADDRESS 8 BIT !! + + +#define TCA9548A_chnl0 0x01 +#define TCA9548A_chnl1 0x02 +#define TCA9548A_chnl2 0x04 +#define TCA9548A_chnl3 0x08 + +#define TCA9548A_All_chnl_OPEN 0xff +#define TCA9548A_All_chnl_CLOSE 0x00 + +#define TCA9548A_chnl_OPEN 1 +#define TCA9548A_chnl_CLOSE 0 + + +uint32_t Reset_n(bool reset); + +//uint32_t Select_Main_WHS_Mux_Channel(bool chnl_stats, uint32_t chnl_number); + uint32_t Select_Main_WHS_Mux_Channel(); uint32_t Block_Main_WHS_Mux_Channel(); - +#define I2C_ID_WHS_CARD 0x03 +#define I2C2_MAIN_MUX_TCA9548A_0xE0 0xE0 //WHS - SD1, SC1 #endif /* DRIVERS_I2C_COMMUNICATION_WHS_CARD_I2C_WHS_MUX_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/TCA9555_Driver.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/TCA9555_Driver.c new file mode 100644 index 000000000..7f399ff59 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/TCA9555_Driver.c @@ -0,0 +1,104 @@ +/* + * Head_IO.c + * + * Created on: 11 11, 2019 + * Author: Shai + */ +#include "include.h" +//#include "WHS_IO.h" +#include <Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/TCA9555_Driver.h> +#include <Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h> +#include <Drivers/I2C_Communication/I2C.h> + + +struct TCA9555_params +{ + uint32_t I2C_id; + uint32_t I2C_address; + uint8_t Config_Reg_PORT_0; +}; + + + + + + +/* + * @brief configure the directions of the I/O pins. + * If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. + * If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output + * @param I2C ID - the bus number ID connected to controller + * @param I2C address - the chip address + * @param Config_dir_PORT_0 + * @param Config_dir_PORT_1 + * @return status - OK or FAIL + */ +uint32_t D_TCA9555ConfigDirection(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS ,uint8_t Config_dir_PORT_0 ,uint8_t Config_dir_PORT_1)//Set GPIO +{ + uint32_t status= OK; + uint8_t Write_Buf[2]; + + Write_Buf[0] = TCA9555_CONFIG_PORT_0; + Write_Buf[1] = Config_dir_PORT_0; + status |= I2C_Write(TCA9555_I2C_bus_number, TCA9555_ADDRESS, Write_Buf, 2); /*status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2);*/ + + + Write_Buf[0] = TCA9555_CONFIG_PORT_1; + Write_Buf[1] = Config_dir_PORT_1; + status |= I2C_Write(TCA9555_I2C_bus_number, TCA9555_ADDRESS, Write_Buf, 2); /*status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2);*/ + return status; +} + +uint32_t D_TCA9555_Read_IO(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS, TCA9555_port_num port_num, uint8_t *value) +{ + uint32_t status= OK; + uint8_t Write_Buf[1]; + uint8_t Read_Buf[1]; + + if (port_num == TCA9555_PORT_0) + { + Write_Buf[0] = TCA9555_PORT_0; + } + else + { + Write_Buf[0] = TCA9555_PORT_1; + } + + status |= I2C_Write(TCA9555_I2C_bus_number, TCA9555_ADDRESS, Write_Buf, 1); //status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2); + delayUs(10);//TODO - check the delay + status |= I2C_Read(TCA9555_I2C_bus_number, TCA9555_ADDRESS + 1, Read_Buf, 1); + *value = Read_Buf[1]; + + return status; +} + +uint32_t D_TCA9555_Write_IO(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS, TCA9555_port_num port_num, uint8_t data) +{ + uint32_t status= OK; + uint8_t Write_Buf[2]; + + Write_Buf[0] = port_num; + Write_Buf[1] = data; + + status |= I2C_Write(TCA9555_I2C_bus_number, TCA9555_ADDRESS, Write_Buf, 2); + return status; +} + + + +//------------------------------ +uint8_t D_WHS_Test_IO() +{ + uint8_t status = PASSED; + +// WHS_IO_Init();//Init + cnofig + + return status; +} + + + + + + + diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/TCA9555_Driver.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/TCA9555_Driver.h new file mode 100644 index 000000000..9f48c57aa --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/TCA9555_Driver.h @@ -0,0 +1,107 @@ +/* + * WHD_IO.h + * + * Created on: Jun 30, 2019 + * Author: Shai + */ + +#ifndef DRIVERS_I2C_COMMUNICATION_WHS_CARD_IO_PORTS_TCA9555_WHS_IO_H_ +#define DRIVERS_I2C_COMMUNICATION_WHS_CARD_IO_PORTS_TCA9555_WHS_IO_H_ + +//COMMAND BYTES +//#define TCA9555_PORT_0 0x00 +//#define TCA9555_PORT_1 0x01 + +#define TCA9555_DIR_OUTPUT 0x00 +#define TCA9555_DIR_INPUT 0x01 + +#define TCA9555_8Pins_INPUT 0xFF +#define TCA9555_8Pins_OUPUT 0x00 + +#define TCA9555_POLARITY_NORMAL 0x00 +#define TCA9555_POLARITY_INV 0x01 + +#define TCA9555_INPUT_PORT_0 0x00 /*reflect the incoming logic levels of PORT_0 pins */ +#define TCA9555_INPUT_PORT_1 0x01 /*reflect the incoming logic levels of PORT_0 pins */ +#define TCA9555_OUTPUT_PORT_0 0x02 /*show the outgoing logic levels of PORT_0 pins defined as outputs */ +#define TCA9555_OUTPUT_PORT_1 0x03 /*show the outgoing logic levels of PORT_1 pins defined as outputs */ +#define TCA9555_POLARITY_PORT_0 0x04 /*allow polarity inversion of PORT_0 pins defined as inputs */ +#define TCA9555_POLARITY_PORT_1 0x05 /*allow polarity inversion of PORT_1 pins defined as inputs */ +#define TCA9555_CONFIG_PORT_0 0x06 /*configure the directions of PORT_0 I/O pins */ +#define TCA9555_CONFIG_PORT_1 0x07 /*configure the directions of PORT_1 I/O pins */ + + +typedef enum +{ + TCA9555_PORT_0 = 0, + TCA9555_PORT_1 +} TCA9555_port_num; + + +typedef union +{ + struct + { + bool TCA9555_bit0 : 1; //0 + bool TCA9555_bit1 : 1; //1 + bool TCA9555_bit2 : 1; //2 + bool TCA9555_bit3 : 1; //3 + bool TCA9555_bit4 : 1; //4 + bool TCA9555_bit5 : 1; //5 + bool TCA9555_bit6 : 1; //6 + bool TCA9555_bit7 : 1; //7 + + }bits; + uint8_t Uchar; +}TCA9555_union; + + +//I2C expander: U3 0x40 +typedef union +{ + struct + { + bool P00 : 1; //P00 + bool P01 : 1; //P01 + bool P02 : 1; //P02 + bool P03 : 1; //P03 + bool P04 : 1; //P04 + bool P05 : 1; //P05 + bool P06 : 1; //P06 + bool P07 : 1; //P07 + + bool p10 : 1; //p10 + bool p11 : 1; //p11 + bool p12 : 1; //p12 + bool p13 : 1; //p13 + bool p14 : 1; //p14 + bool p15 : 1; //p15 + bool p16 : 1; //p16 + bool p17 : 1; //p17 + }bits; + unsigned char uchar[2]; + unsigned short ushort; +}IO_port_name; + + +extern IO_port_name IO_Port_name; + + +/* +uint32_t D_TCA9555_Config_Input_Port0( uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS, uint8_t TCA9555_Port); +uint32_t D_TCA9555_Config_Input_Port1( uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS); +uint32_t D_TCA9555_Config_Output_Port0(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS); +uint32_t D_TCA9555_Config_Output_Port1(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS); +uint32_t D_TCA9555_Config_Polarity_Port0(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS); +uint32_t D_TCA9555_Config_Polarity_Port1(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS); +*/ + +uint32_t D_TCA9555_Write_IO(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS, TCA9555_port_num port_num, uint8_t data); +uint32_t D_TCA9555_Read_IO(uint8_t TCA9555_I2C_bus_number, uint8_t TCA9555_ADDRESS, TCA9555_port_num port_num, uint8_t *value); +uint32_t D_TCA9555ConfigDirection(uint8_t TCA9555_I2C_bus_number,uint8_t TCA9555_ADDRESS ,uint8_t Config_Reg_PORT_0 ,uint8_t Config_Reg_PORT_1); +uint32_t D_TCA9555_IO_Init(); +uint8_t D_TCA9555_Test_IO(); + +//------------------------------ + +#endif /* DRIVERS_I2C_COMMUNICATION_WHS_CARD_IO_PORTS_TCA9555_WHS_IO_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.c new file mode 100644 index 000000000..921477f12 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.c @@ -0,0 +1,265 @@ +/* + * Head_IO.c + * + * Created on: Jun 30, 2019 + * Author: avi + */ +#include "include.h" +//#include "WHS_IO.h" +#include <Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.h> +#include <Drivers/I2C_Communication/WHS_Card/I2C_WHS_Mux.h> +#include <Drivers/I2C_Communication/I2C.h> +//#include <Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.h> +/* +GPIO TCA9555RTWR +ADDR 0x40 +ADDR 0x42 +*/ + +WHS_I2C_EXP1_0x40 Whs_I2C_EXP1_0x40; +WHS_I2C_EXP2_0x42 Whs_I2C_EXP2_0x42; + +# define U3_I2C_ADDR 0x40 +# define U4_I2C_ADDR 0x42 + +uint32_t WHS_TCA9555Config(uint8_t TCA9555_ADDRESS)//Set GPIO +{ + uint32_t status= OK; + uint8_t Config_Reg_PORT_0; + uint8_t Config_Reg_PORT_1; + uint8_t Write_Buf[2]; + TCA9555_union config_bits; + + switch (TCA9555_ADDRESS) + { + case U3_I2C_ADDR: + Config_Reg_PORT_0 = TCA9555_8Pins_OUPUT; + Config_Reg_PORT_1 = TCA9555_8Pins_INPUT; + break; + case U4_I2C_ADDR: + Config_Reg_PORT_0 = TCA9555_8Pins_OUPUT; + Config_Reg_PORT_1 = TCA9555_8Pins_INPUT; + break; + default : + return ERROR; + + } + +/* if(TCA9555_ADDRESS == 0x40) + { + + } + else + if(TCA9555_ADDRESS == 0x42) + { + Config_Reg_PORT_0 = TCA9555_8Pins_OUPUT; + Config_Reg_PORT_1 = TCA9555_8Pins_OUPUT; + } + else + if(TCA9555_ADDRESS == 0x44) + { + + Config_Reg_PORT_0 = TCA9555_8Pins_INPUT; + Config_Reg_PORT_1 = TCA9555_8Pins_OUPUT; + } + else + if(TCA9555_ADDRESS == 0x46) + { + config_bits.bits.TCA9555_bit0 = TCA9555_DIR_INPUT; + config_bits.bits.TCA9555_bit1 = TCA9555_DIR_INPUT; + config_bits.bits.TCA9555_bit2 = TCA9555_DIR_INPUT; + config_bits.bits.TCA9555_bit3 = TCA9555_DIR_INPUT; + config_bits.bits.TCA9555_bit4 = TCA9555_DIR_INPUT; + config_bits.bits.TCA9555_bit5 = TCA9555_DIR_INPUT; + config_bits.bits.TCA9555_bit6 = TCA9555_DIR_INPUT; + config_bits.bits.TCA9555_bit7 = TCA9555_DIR_OUTPUT; + + Config_Reg_PORT_0 = config_bits.Uchar; + + config_bits.bits.TCA9555_bit0 = TCA9555_DIR_INPUT;//8 + config_bits.bits.TCA9555_bit1 = TCA9555_DIR_INPUT;//9 + config_bits.bits.TCA9555_bit2 = TCA9555_DIR_OUTPUT;//10 + config_bits.bits.TCA9555_bit3 = TCA9555_DIR_OUTPUT;//11 + config_bits.bits.TCA9555_bit4 = TCA9555_DIR_INPUT;//12 + config_bits.bits.TCA9555_bit5 = TCA9555_DIR_INPUT;//13 + config_bits.bits.TCA9555_bit6 = TCA9555_DIR_INPUT;//14 + config_bits.bits.TCA9555_bit7 = TCA9555_DIR_INPUT;//15 + + Config_Reg_PORT_1 = config_bits.Uchar; + } + + else + return ERROR; +*/ + + Write_Buf[0] = TCA9555_CONFIG_PORT_0; + Write_Buf[1] = Config_Reg_PORT_0; +// status |= Select_Main_WHS_Mux_Channel(); //status |= Select_Main_Head_Mux_Channel(); + status |= I2C_Write(I2C_ID_WHS_CARD, TCA9555_ADDRESS, Write_Buf, 2); //status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2); + + + Write_Buf[0] = TCA9555_CONFIG_PORT_1; + Write_Buf[1] = Config_Reg_PORT_1; +// status |= Select_Main_WHS_Mux_Channel(); //status |= Select_Main_Head_Mux_Channel(); + status |= I2C_Write(I2C_ID_WHS_CARD, TCA9555_ADDRESS, Write_Buf, 2); //status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2); + + return OK; + +} + +uint32_t WHS_IO_Init() +{ + uint32_t status = OK; + uint8_t i = 0; + + + //Set all the active low bits to "1" and all the active high bits to "0" + + for(i=0;i<2;i++) + { + Whs_I2C_EXP1_0x40.uchar[i] = 0x00; +// WHS_I2C_EXP2_0x42.uchar[i] = 0x00; +// Head_I2C_EXP1_0x44.uchar[i] = 0x01; +// Head_I2C_EXP1_0x46.uchar[i] = 0x00; + } + + Whs_I2C_EXP1_0x40.bits.OUTPUT_ACTLOW_PT_RSTn = 0x01; + Whs_I2C_EXP1_0x40.bits.OUTPUT_PT_SEL = 1; + Whs_I2C_EXP1_0x40.bits.OUTPUT_ACTLOW_AUXn = 1; + Whs_I2C_EXP1_0x40.bits.OUTPUT_ACTLOW_LDACn = 1; + Whs_I2C_EXP1_0x40.bits.OUTPUT_FANS_ON = 1; + Whs_I2C_EXP1_0x40.bits.OUTPUT_FANS_LATCH_RST = 1; + Whs_I2C_EXP1_0x40.bits.OUTPUT_I2CSW_RST = 1; + Whs_I2C_EXP1_0x40.bits.OUTPUT_PUMP_ON = 1; + + + + + + + + + + TCA9555Config(0x40); + TCA9555Config(0x42); +// TCA9555Config(0x44); +// TCA9555Config(0x46); + + return status; +} + + +uint32_t WHS_Write_IO_Reg(uint8_t TCA9555_ADDRESS) +{ + uint32_t status= OK; + uint8_t Write_Buf[2]; + + if(TCA9555_ADDRESS == 0x40) + { +// Write_Buf[0] = TCA9555_OUTPUT_PORT_0; +// Write_Buf[1] = WHS_I2C_EXP1_0x40.uchar[0]; +// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2); +// +// Write_Buf[0] = TCA9555_OUTPUT_PORT_1; +// Write_Buf[1] = Head_I2C_EXP1_0x40.uchar[1]; +// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2); + } + else + if(TCA9555_ADDRESS == 0x42) + { +// Write_Buf[0] = TCA9555_OUTPUT_PORT_0; +// Write_Buf[1] = WHS_I2C_EXP1_0x42.uchar[0]; +//// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_WHS_CARD, TCA9555_ADDRESS, Write_Buf, 2); +// +// Write_Buf[0] = TCA9555_OUTPUT_PORT_1; +// Write_Buf[1] = WHS_I2C_EXP1_0x42.uchar[1]; +//// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_WHS_CARD, TCA9555_ADDRESS, Write_Buf, 2); + } +// else +// if(TCA9555_ADDRESS == 0x46) +// { +// Write_Buf[0] = TCA9555_OUTPUT_PORT_0; +// Write_Buf[1] = WHS_I2C_EXP1_0x46.uchar[0] & BIT7; +//// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_WHS_CARD, TCA9555_ADDRESS, Write_Buf, 2); +// +// Write_Buf[0] = TCA9555_OUTPUT_PORT_1; +// Write_Buf[1] = Head_I2C_EXP1_0x46.uchar[1] & (BIT11 | BIT12) ; +// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 2); +// } + else + status = ERROR; + + return status; +} + +uint32_t WHS_Read_IO_Reg(uint8_t TCA9555_ADDRESS) +{ + uint32_t status= OK; + uint8_t Write_Buf[1] = {0}; + uint8_t Read_Buf[1] = {0}; + + if(TCA9555_ADDRESS == 0x40) + { +// Write_Buf[0] = TCA9555_INPUT_PORT_0; +// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 1); +// delayUs(10);//TODO - check the delay +// status |= I2C_Read(I2C_ID_HEAD_CARD, TCA9555_ADDRESS + 1, Read_Buf, 1); +// WHS_I2C_EXP1_0x44.uchar[0] = Read_Buf[0]; +// +// Write_Buf[0] = TCA9555_INPUT_PORT_1; +// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 1); +// delayUs(10);//TODO - check the delay +// status |= I2C_Read(I2C_ID_HEAD_CARD, TCA9555_ADDRESS + 1, Read_Buf, 1); +// +// Head_I2C_EXP1_0x44.uchar[1] = Read_Buf[0]; + } +// else +// if(TCA9555_ADDRESS == 0x42) +// { +// Write_Buf[0] = TCA9555_INPUT_PORT_0; +// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 1); +// delayUs(10);//TODO - check the delay +// status |= I2C_Read(I2C_ID_HEAD_CARD, TCA9555_ADDRESS + 1, Read_Buf, 1); +// Head_I2C_EXP1_0x46.uchar[0] = (Read_Buf[0] & ~BIT7); +// +// Write_Buf[0] = TCA9555_INPUT_PORT_1; +// status |= Select_Main_Head_Mux_Channel(); +// status |= I2C_Write(I2C_ID_HEAD_CARD, TCA9555_ADDRESS, Write_Buf, 1); +// delayUs(10);//TODO - check the delay +// status |= I2C_Read(I2C_ID_HEAD_CARD, TCA9555_ADDRESS + 1, Read_Buf, 1); +// +// Head_I2C_EXP1_0x46.uchar[1] |= (Read_Buf[0]& ~(BIT11 | BIT12)) ; +// } + else + status = ERROR; + + return status; +} + + + +//------------------------------ +uint8_t WHS_Test_IO() +{ + uint8_t status = PASSED; + + WHS_IO_Init();//Init + cnofig + + return status; +} + + + + + + + diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.h new file mode 100644 index 000000000..381ae8536 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/IO_Ports_TCA9555/WHS_IO.h @@ -0,0 +1,128 @@ +/* + * WHD_IO.h + * + * Created on: Jun 30, 2019 + * Author: Shai + */ + +#ifndef DRIVERS_I2C_COMMUNICATION_WHS_CARD_IO_PORTS_TCA9555_WHS_IO_H_ +#define DRIVERS_I2C_COMMUNICATION_WHS_CARD_IO_PORTS_TCA9555_WHS_IO_H_ + +//COMMAND BYTES + + + + + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + bool TCA9555_bit0 : 1; //0 + bool TCA9555_bit1 : 1; //1 + bool TCA9555_bit2 : 1; //2 + bool TCA9555_bit3 : 1; //3 + bool TCA9555_bit4 : 1; //4 + bool TCA9555_bit5 : 1; //5 + bool TCA9555_bit6 : 1; //6 + bool TCA9555_bit7 : 1; //7 + + }bits; + uint8_t Uchar; +}TCA9555_union; + + +//I2C expander: U3 0x40 +typedef union +{ + struct + { + bool OUTPUT_ACTLOW_PT_RSTn : 1; //P00 + bool OUTPUT_PT_SEL : 1; //P01 + bool OUTPUT_ACTLOW_AUXn : 1; //P02 + bool OUTPUT_ACTLOW_LDACn : 1; //P03 + bool OUTPUT_FANS_ON : 1; //P04 + bool OUTPUT_FANS_LATCH_RST : 1; //P05 + bool OUTPUT_I2CSW_RST : 1; //P06 + bool OUTPUT_PUMP_ON : 1; //P07 + + bool IN_FANS_BREAK : 1; //p10 + bool IN_FAN_ALART_12 : 1; //p11 + bool IN_FAN_ALART_34 : 1; //p12 + bool IN_FAN_ALART_56 : 1; //p13 + bool IN_NC_p14 : 1; //p14 + bool IN_NC_p15 : 1; //p15 + bool IN_NC_p16 : 1; //p16 + bool IN_NC_p17 : 1; //p17 + }bits; + unsigned char uchar[2]; + unsigned short ushort; +}WHS_I2C_EXP1_0x40; + +//I2C expander: U4 0x42 +typedef union +{ + struct + { + bool OUTPUT_ACTLOW_DE_REn : 1; //P00 + bool OUTPUT_NC_P01 : 1; //P01 + bool OUTPUT_NC_P02 : 1; //P02 + bool OUTPUT_RST_100K : 1; //P03 + bool OUTPUT_VALV1_DIR : 1; //P04 + bool OUTPUT_VALV1_EN : 1; //P05 + bool OUTPUT_VALV2_DIR : 1; //P06 + bool OUTPUT_VALV2_EN : 1; //P07 + + bool OUTPUT_RST_I2C_485 : 1; //p10 + bool OUTPUT_NC_p11 : 1; //p11 + bool OUTPUT_NC_p12 : 1; //p12 + bool OUTPUT_NC_p13 : 1; //p13 + bool OUTPUT_NC_p14 : 1; //p14 + bool OUTPUT_NC_p15 : 1; //p15 + bool OUTPUT_NC_p16 : 1; //p16 + bool OUTPUT_NC_p17 : 1; //p17 + }bits; + unsigned char uchar[2]; + unsigned short ushort; +}WHS_I2C_EXP2_0x42; + + + + + + + + +extern WHS_I2C_EXP1_0x40 Whs_I2C_EXP1_0x40; +extern WHS_I2C_EXP2_0x42 Whs_I2C_EXP2_0x42; + + +/* +extern HEAD_I2C_EXP3_0x44 Head_I2C_EXP1_0x44; +extern HEAD_I2C_EXP4_0x46 Head_I2C_EXP1_0x46; +*/ +uint32_t WHS_IO_Init(); +uint32_t WHS_Write_IO_Reg(uint8_t TCA9555_ADDRESS); +uint32_t WHS_Read_IO_Reg(uint8_t TCA9555_ADDRESS); + +//------------------------------ +uint8_t WHS_Test_IO(); + +#endif /* DRIVERS_I2C_COMMUNICATION_WHS_CARD_IO_PORTS_TCA9555_WHS_IO_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/ADS122X04.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/ADS122X04.h new file mode 100644 index 000000000..114e6db24 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/ADS122X04.h @@ -0,0 +1,498 @@ +#ifndef ADS122X04_H_ +#define ADS122X04_H_ +/*************************************************************************************************************************************************/ +/*! ADS122U04.h +* ADS122C04.h +* Header file for ADS122x04.c library software +* +*/ +/************************************************************************************************************************************************** +* Copyright ?2017 Texas Instruments Incorporated - http://www.ti.com/ * +*************************************************************************************************************************************************** +* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * +* * +* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * +* * +* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the * +* documentation and/or other materials provided with the distribution. * +* * +* Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived * +* from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +**************************************************************************************************************************************************/ +#define _ADS122C04_ +//#define _ADS122U04_ + +#define __BIT_FIELD__ + +#ifdef __CPLUSPLUS +extern "C" { +#endif + + +//#include "driverlib.h" + +// ADS122U04, Table 15 and C04 Datasheets +#define ADS122X_RESET_CMD 0x06 //0000 011x Reset +#define ADS122X_START_CMD 0x08 //0000 100x Start/Sync +#define ADS122X_POWERDOWN_CMD 0x02 //0000 001x PowerDown +#define ADS122X_RDATA_CMD 0x10 //0001 xxxx RDATA +#define ADS122X_RREG_CMD 0x20 //0010 rrrx Read REG rrr= register address 000 to 100 in ADS122U04, 0010 rrxx in ADS122C04 +#define ADS122X_WREG_CMD 0x40 //0100 rrrx Write REG rrr= register address 000 to 100 in ADS122U04, 0010 rrxx in ADS122C04 + +#ifdef _ADS122U04_ +#define SHIFT_BITS 1 +#else +#define SHIFT_BITS 2 +#endif +#define ADS122X_WRITE_CMD(reg) (ADS122X_WREG_CMD + (reg << SHIFT_BITS)) //Shift is 1 bit in ADS122U04 vs 2-bit in ADS122C04 +#define ADS122X_READ_CMD(reg) (ADS122X_RREG_CMD + (reg << SHIFT_BITS)) //Shift is 1 bit in ADS122U04 vs 2-bit in ADS122C04 + + +#define ADS122X_CONFIG_0_REG 0 +#define ADS122X_CONFIG_1_REG 1 +#define ADS122X_CONFIG_2_REG 2 +#define ADS122X_CONFIG_3_REG 3 + +#ifdef _ADS122U04_ +#define ADS122X_CONFIG_4_REG 4 //Reg. 4 in ADS122U04 +#endif + + +// Configuration Register 0 Settings 00h +#define ADS122X_MUX_MASK 0xf0 +#ifdef __BIT_FIELD__ +#define ADS122X_MUX_SHIFT 0 +#else +#define ADS122X_MUX_SHIFT 4 +#endif //__BIT_FIELD__ + +//modified for ADS122x04 vs. ADS1220 +//MUX +/* +#define ADS122X_MUX_AIN0_AIN1 (0x0 << ADS122X_MUX_SHIFT) //default +#define ADS122X_MUX_AIN0_AIN2 (0x1 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN0_AIN3 (0x2 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN1_AIN0 (0x3 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN1_AIN2 (0x4 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN1_AIN3 (0x5 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN2_AIN3 (0x6 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN3_AIN2 (0x7 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN0_AVSS (0x8 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN1_AVSS (0x9 << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN2_AVSS (0xa << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AIN3_AVSS (0xb << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_REFPmREFN (0xc << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_AVDDmAVSS (0xd << ADS122X_MUX_SHIFT) +#define ADS122X_MUX_SHORTED (0xe << ADS122X_MUX_SHIFT) +*/ +#define ADS122X_MUX_AIN0_AIN1 0x0 //default +#define ADS122X_MUX_AIN0_AIN2 0x1 +#define ADS122X_MUX_AIN0_AIN3 0x2 +#define ADS122X_MUX_AIN1_AIN0 0x3 +#define ADS122X_MUX_AIN1_AIN2 0x4 +#define ADS122X_MUX_AIN1_AIN3 0x5 +#define ADS122X_MUX_AIN2_AIN3 0x6 +#define ADS122X_MUX_AIN3_AIN2 0x7 +#define ADS122X_MUX_AIN0_AVSS 0x8 +#define ADS122X_MUX_AIN1_AVSS 0x9 +#define ADS122X_MUX_AIN2_AVSS 0xa +#define ADS122X_MUX_AIN3_AVSS 0xb +#define ADS122X_MUX_REFPmREFN 0xc +#define ADS122X_MUX_AVDDmAVSS 0xd +#define ADS122X_MUX_SHORTED 0xe + +#define ADS122X_GAIN_MASK 0xe +#ifdef __BIT_FIELD__ +#define ADS122X_GAIN_SHIFT 0 +#else +#define ADS122X_GAIN_SHIFT 1 +#endif //__BIT_FIELD__ + +/* +#define ADS122X_GAIN_1 (0x0 << ADS122X_GAIN_SHIFT) +#define ADS122X_GAIN_2 (0x1 << ADS122X_GAIN_SHIFT) +#define ADS122X_GAIN_4 (0x2 << ADS122X_GAIN_SHIFT) +#define ADS122X_GAIN_8 (0x3 << ADS122X_GAIN_SHIFT) +#define ADS122X_GAIN_16 (0x4 << ADS122X_GAIN_SHIFT) +#define ADS122X_GAIN_32 (0x5 << ADS122X_GAIN_SHIFT) +#define ADS122X_GAIN_64 (0x6 << ADS122X_GAIN_SHIFT) +#define ADS122X_GAIN_128 (0x7 << ADS122X_GAIN_SHIFT) +*/ + +#define ADS122X_GAIN_1 0x0 +#define ADS122X_GAIN_2 0x1 +#define ADS122X_GAIN_4 0x2 +#define ADS122X_GAIN_8 0x3 +#define ADS122X_GAIN_16 0x4 +#define ADS122X_GAIN_32 0x5 +#define ADS122X_GAIN_64 0x6 +#define ADS122X_GAIN_128 0x7 + + +#define ADS122X_PGA_BYPASS 1 +#define ADS122X_USE_PGA 0 + +#ifdef _ADS122U04_ +#define ADS122X_AUTO_READ 1 +#define ADS122X_MAN_READ 0 +#endif +// Configuration Register 1 Settings 01h + +#define ADS122X_DATA_RATE_MASK 0xe0 +#ifdef __BIT_FIELD__ +#define ADS122X_DATA_RATE_SHIFT 0 +#else +#define ADS122X_DATA_RATE_SHIFT 5 +#endif //__BIT_FIELD__ + +// Turbo mode = Normal mode * 2 (Samples per Second) +// Normal mode +/* +#define ADS122X_DATA_RATE_20SPS (0 << ADS122X_DATA_RATE_SHIFT) +#define ADS122X_DATA_RATE_45SPS (1 << ADS122X_DATA_RATE_SHIFT) +#define ADS122X_DATA_RATE_90SPS (2 << ADS122X_DATA_RATE_SHIFT) +#define ADS122X_DATA_RATE_175SPS (3 << ADS122X_DATA_RATE_SHIFT) +#define ADS122X_DATA_RATE_330SPS (4 << ADS122X_DATA_RATE_SHIFT) +#define ADS122X_DATA_RATE_600SPS (5 << ADS122X_DATA_RATE_SHIFT) +#define ADS122X_DATA_RATE_1000SPS (6 << ADS122X_DATA_RATE_SHIFT) +*/ +#define ADS122X_DATA_RATE_20SPS 0 +#define ADS122X_DATA_RATE_45SPS 1 +#define ADS122X_DATA_RATE_90SPS 2 +#define ADS122X_DATA_RATE_175SPS 3 +#define ADS122X_DATA_RATE_330SPS 4 +#define ADS122X_DATA_RATE_600SPS 5 +#define ADS122X_DATA_RATE_1000SPS 6 + + +#define ADS122X_OP_MODE_MASK 0x10 +#ifdef __BIT_FIELD__ +#define ADS122X_OP_MODE_SHIFT 0 +#else +#define ADS122X_OP_MODE_SHIFT 4 +#endif //__BIT_FIELD__ + +/* +#define ADS122X_OP_MODE_NORMAL (0 << ADS122X_OP_MODE_SHIFT) +#define ADS122X_OP_MODE_TURBO (1 << ADS122X_OP_MODE_SHIFT) +*/ +#define ADS122X_OP_MODE_NORMAL 0 +#define ADS122X_OP_MODE_TURBO 1 + +#define ADS122X_CONVERSION_MODE_MASK 0x4 +#define ADS122X_CONVERSION_SINGLE_SHOT 0x0 +#ifdef __BIT_FIELD__ +#define ADS122X_CONVERSION_CONTINUOUS 0x1 +#else +#define ADS122X_CONVERSION_CONTINUOUS 0x4 +#endif //__BIT_FIELD__ + + + +#define ADS122X_TEMP_SENSOR_MASK 0x2 +#ifdef __BIT_FIELD__ +#define ADS122X_TEMP_SENSOR_ON 0x1 +#else +#define ADS122X_TEMP_SENSOR_ON 0x2 +#endif //__BIT_FIELD__ +#define ADS122X_TEMP_SENSOR_OFF 0x0 + +#define ADS122X_BURN_OUT_MASK 0x1 +#define ADS122X_BURN_OUT_CURRENT_ON 0x1 +#define ADS122X_BURN_OUT_CURRENT_OFF 0x0 + +// Configuration Register 2 Settings 02h + +#define ADS122X_VREF_MASK 0x06 +#ifdef __BIT_FIELD__ +#define ADS122X_VREF_SHIFT 0 +#else +#define ADS122X_VREF_SHIFT 1 +#endif //__BIT_FIELD__ + +/* +#define ADS122X_VREF_INTERNAL (0 << ADS122X_VREF_SHIFT) //2.048V internal +#define ADS122X_VREF_EXT_REF0_PINS (1 << ADS122X_VREF_SHIFT) //REFp and REFn external +#define ADS122X_VREF_EXT_REF1_PINS (2 << ADS122X_VREF_SHIFT) //Analog Supply AVDD and AVSS +#define ADS122X_VREF_AVDD (3 << ADS122X_VREF_SHIFT) //Analog Supply AVDD and AVSS +*/ +#define ADS122X_VREF_INTERNAL 0 //2.048V internal +#define ADS122X_VREF_EXT_REF0_PINS 1 //REFp and REFn external +#define ADS122X_VREF_EXT_REF1_PINS 2 //Analog Supply AVDD and AVSS +#define ADS122X_VREF_AVDD 3 //Analog Supply AVDD and AVSS + + +//28.9.17 fix PSW and rest of bit fields +#define ADS122X_LOW_SIDE_POWER_MASK 0x04 +#define ADS122X_LOW_SIDE_POWER_OPEN 0x00 +#ifdef __BIT_FIELD__ +#define ADS122X_LOW_SIDE_POWER_CLOSES 0x01 +#else +#define ADS122X_LOW_SIDE_POWER_CLOSES 0x04 +#endif //__BIT_FIELD__ + + +#define ADS122X_IDAC_CURRENT_MASK 0x07 +#ifdef __BIT_FIELD__ +#define ADS122X_IDAC_CURRENT_SHIFT 0 +#else +#define ADS122X_IDAC_CURRENT_SHIFT 0 +#endif //__BIT_FIELD__ + +/* +#define ADS122X_IDAC_CURRENT_OFF (0 << ADS122X_IDAC_CURRENT_SHIFT) +#define ADS122X_IDAC_CURRENT_10_UA (1 << ADS122X_IDAC_CURRENT_SHIFT) +#define ADS122X_IDAC_CURRENT_50_UA (2 << ADS122X_IDAC_CURRENT_SHIFT) +#define ADS122X_IDAC_CURRENT_100_UA (3 << ADS122X_IDAC_CURRENT_SHIFT) +#define ADS122X_IDAC_CURRENT_250_UA (4 << ADS122X_IDAC_CURRENT_SHIFT) +#define ADS122X_IDAC_CURRENT_500_UA (5 << ADS122X_IDAC_CURRENT_SHIFT) +#define ADS122X_IDAC_CURRENT_1000_UA (6 << ADS122X_IDAC_CURRENT_SHIFT) +#define ADS122X_IDAC_CURRENT_1500_UA (7 << ADS122X_IDAC_CURRENT_SHIFT) +*/ +#define ADS122X_IDAC_CURRENT_OFF 0 +#define ADS122X_IDAC_CURRENT_10_UA 1 +#define ADS122X_IDAC_CURRENT_50_UA 2 +#define ADS122X_IDAC_CURRENT_100_UA 3 +#define ADS122X_IDAC_CURRENT_250_UA 4 +#define ADS122X_IDAC_CURRENT_500_UA 5 +#define ADS122X_IDAC_CURRENT_1000_UA 6 +#define ADS122X_IDAC_CURRENT_1500_UA 7 + +// Configuration Register 3 Settings 03h + +#define ADS122X_IDAC1_MUX_MASK 0xe0 +#ifdef __BIT_FIELD__ +#define ADS122X_IDAC1_MUX_SHIFT 0 +#else +#define ADS122X_IDAC1_MUX_SHIFT 5 +#endif //__BIT_FIELD__ + + +#define ADS122X_BCS_CURRENT_SOURCES_OFF 0 +#define ADS122X_BCS_CURRENT_SOURCES_ON 1 + +#define ADS122X_CRC_DISABLED 0 + +#define ADS122X_DCNT_CONVERSION_COUNTER_DISABLED 0 + +#define ADS122X_DRDY_NO_NEW_CONVERSION 0 + +#define ADS122X_RESERVED_WRITE_0 0 +/* +#define ADS122X_IDAC1_DISABLED (0 << ADS122X_IDAC1_MUX_SHIFT) +#define ADS122X_IDAC1_AIN0 (1 << ADS122X_IDAC1_MUX_SHIFT) +#define ADS122X_IDAC1_AIN1 (2 << ADS122X_IDAC1_MUX_SHIFT) +#define ADS122X_IDAC1_AIN2 (3 << ADS122X_IDAC1_MUX_SHIFT) +#define ADS122X_IDAC1_AIN3 (4 << ADS122X_IDAC1_MUX_SHIFT) +#define ADS122X_IDAC1_REFP0 (5 << ADS122X_IDAC1_MUX_SHIFT) +#define ADS122X_IDAC1_REFN0 (6 << ADS122X_IDAC1_MUX_SHIFT) +*/ +#define ADS122X_IDAC1_DISABLED 0 +#define ADS122X_IDAC1_AIN0 1 +#define ADS122X_IDAC1_AIN1 2 +#define ADS122X_IDAC1_AIN2 3 +#define ADS122X_IDAC1_AIN3 4 +#define ADS122X_IDAC1_REFP0 5 +#define ADS122X_IDAC1_REFN0 6 + + +#define ADS122X_IDAC2_MUX_MASK 0x1c +#ifdef __BIT_FIELD__ +#define ADS122X_IDAC2_MUX_SHIFT 0 +#else +#define ADS122X_IDAC2_MUX_SHIFT 2 +#endif //__BIT_FIELD__ + +/* +#define ADS122X_IDAC2_DISABLED (0 << ADS122X_IDAC2_MUX_SHIFT) +#define ADS122X_IDAC2_AIN0 (1 << ADS122X_IDAC2_MUX_SHIFT) +#define ADS122X_IDAC2_AIN1 (2 << ADS122X_IDAC2_MUX_SHIFT) +#define ADS122X_IDAC2_AIN2 (3 << ADS122X_IDAC2_MUX_SHIFT) +#define ADS122X_IDAC2_AIN3 (4 << ADS122X_IDAC2_MUX_SHIFT) +#define ADS122X_IDAC2_REFP0 (5 << ADS122X_IDAC2_MUX_SHIFT) +#define ADS122X_IDAC2_REFN0 (6 << ADS122X_IDAC2_MUX_SHIFT) +*/ +#define ADS122X_IDAC2_DISABLED 0 +#define ADS122X_IDAC2_AIN0 1 +#define ADS122X_IDAC2_AIN1 2 +#define ADS122X_IDAC2_AIN2 3 +#define ADS122X_IDAC2_AIN3 4 +#define ADS122X_IDAC2_REFP0 5 +#define ADS122X_IDAC2_REFN0 6 + + +#define ADS122X_DOUT_DRDY_MASK 0x2 +#define ADS122X_DRDY_ON_DOUT_DRDY 0x2 +#define ADS122X_DRDY_ON_DRDY_ONLY 0x0 + +// GPIO Configure +#ifdef _ADS122U04_ + #define ADS122X_GPIO0 0 + #define ADS122X_GPIO1 1 + #define ADS122X_GPIO2 2 + + #define ADS122X_GPIO_INPUT 0 + #define ADS122X_GPIO_OUTPUT 1 + #define ADS122X_GPIO_DRDY 3 // when configure as an output +#endif + +/* +// Bit field type register configuration +// Configuration Map register ADS122x04 +//--------------Address 0x00--------------------------------- +struct CONFIG_REG_0{ + uint8_t PGA_BYPASS:1; // 0 + uint8_t GAIN:3; // 1-3 + uint8_t MUX:4; // 4-7 +}; +union CONFIG_REG_0_U { + uint8_t all; + struct CONFIG_REG_0 bit; +}; + +//MS Reg. 01-04 adjusted +//--------------Address 0x01--------------------------------- +struct CONFIG_REG_1{ + uint8_t TS:1; // 0 + uint8_t VREF:2; // 1-2 + uint8_t CMBIT:1; // 3 + uint8_t MODE:1; // 4 + uint8_t DR:3; // 5-7 +}; +union CONFIG_REG_1_U { + uint8_t all; + struct CONFIG_REG_1 bit; +}; +//--------------Address 0x02--------------------------------- +struct CONFIG_REG_2{ + uint8_t IDAC:3; // 0-2 + uint8_t BCS:1; // 3 + uint8_t CRC:2; // 4-5 + uint8_t DCNT:1; // 6 + uint8_t DRDY:1; // 7 +}; +union CONFIG_REG_2_U { + uint8_t all; + struct CONFIG_REG_2 bit; +}; + +//--------------Address 0x03--------------------------------- +struct CONFIG_REG_3{ + #ifdef _ADS122U04_ + uint8_t AUTOUART:1; // 0 + uint8_t ZERO:1; // 1 + #else + uint8_t ZERO:2; // 1 + #endif + uint8_t I2MUX:3; // 2-4 + uint8_t I1MUX:3; // 5-7 +}; +union CONFIG_REG_3_U { + uint8_t all; + struct CONFIG_REG_3 bit; +}; + +//MS extended with Reg.0x04 + +//--------------Address 0x04--------------------------------- +#ifdef _ADS122U04_ +struct CONFIG_REG_4{ + uint8_t GPIO0DAT:1; // 0 + uint8_t GPIO1DAT:1; // 1 + uint8_t GPIO2DAT:1; // 2 + uint8_t GPIO2SEL:1; // 3 + uint8_t GPIO0DIR:1; // 4 + uint8_t GPIO1DIR:1; // 5 + uint8_t GPIO2DIR:1; // 6 + uint8_t ZERO:1; // 7 +}; +union CONFIG_REG_4_U { + uint8_t all; + struct CONFIG_REG_4 bit; +}; +#endif +typedef struct ADS122XReg{ + union CONFIG_REG_0_U reg0; + union CONFIG_REG_1_U reg1; + union CONFIG_REG_2_U reg2; + union CONFIG_REG_3_U reg3; + #ifdef _ADS122U04_ + union CONFIG_REG_4_U reg4; // only on ADS122U04, not in ADS122C04 + #endif +}ADS122XReg_t; + +// UART Communication Prototypes +#ifdef _ADS122U04_ +#define UART_SYNC_WORD (0x55) +#else +#define ADS122C04_I2C_ADDR (0x40) //ADS122C04 I2C SLAVE ADDRESS +#endif + +// Port +// SPI not used +// I2C to ADS122C04 is EUSCI_A3_BASE +// UART to ADS122U04 is EUSCI_A3_BASE +#ifdef _ADS122U04_ +#define ADS122X_UART EUSCI_A3_BASE +#else +#define ADS122X_I2C EUSCI_B0_BASE +#endif +// ************************************************************************************************************* / +// * PROTOTYPES * / +// ************************************************************************************************************* / + +typedef struct{ + uint8_t dataRate; + uint8_t gainLevel; + uint8_t convMode; + uint8_t opMode; + uint8_t inputMux; + uint8_t selectVref; + uint8_t routeIDAC1; + uint8_t routeIDAC2; + uint8_t idacCurrent; + uint8_t pgaBypass; + #ifdef _ADS122U04_ + uint8_t dataOutMode; + #endif + uint8_t tempSensorEn; +}ADS122X_initParam; + + +void ADS122X_init(ADS122X_initParam *param); + +void ADS122X_reset(void); +void ADS122X_start(void); +void ADS122X_powerdown(void); +void ADS122X_sendReadDataCommand(void); +void ADS122X_writeReg(uint8_t reg, uint8_t writeValue); +void ADS122X_readReg(uint8_t reg, uint8_t *readValue); + +void ADS122X_isDataReady(uint8_t *isDataReady); +void ADS122X_getConversionData(uint32_t *conversionData); +void ADS122X_getConversionDataWithCount(uint32_t *conversionData, uint8_t *count); + +void ADS122X_enableDataCounter(void); +void ADS122X_disableDataCounter(void); +void ADS122X_enableInternalTempSensor(void); +void ADS122X_disableInternalTempSensor(void); +void ADS122X_enableBurnOutCurrent(void); +void ADS122X_disableBurnOutCurrent(void); +#ifdef _ADS122U04_ +void ADS122X_setGpioFunction(uint8_t gpio, uint8_t function); // DRDY only for GPIO2 +void ADS122X_setGpioValue(uint8_t gpio, uint8_t value); +void ADS122X_getGpioValue(uint8_t gpio, uint8_t *value); +#endif + +#ifdef __CPLUSPLUS +} +#endif +*/ +#endif /* ADS122X_H_ */ diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/PT100_ADC.c b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/PT100_ADC.c new file mode 100644 index 000000000..1f1b74dec --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/PT100_ADC.c @@ -0,0 +1,392 @@ +/* + * PT100_ADC.c + * + * Created on: Jun 30, 2019 + * Author: avi + */ + +/* +PT100 ADS122C04IRTE +ADDR 0x80 +ADDR 0x81 +ADDR 0x82 +ADDR 0x83 +ADDR 0x84 +ADDR 0x85 +ADDR 0x86 +ADDR 0x87 +*/ + +#include "include.h" +#include "modules/control/millisecTask.h" +#include "Modules/AlarmHandling/AlarmHandling.h" +#include "PT100_ADC.h" +#include "ADS122X04.h" +//#include "PT100RTD.h" +#include <DataDef.h> +#include "../I2C_Head_Mux.h" +#include "drivers/I2C_Communication/I2C.h" + +uint32_t I2C_ADC_ADS122C04_SLAVE_ADD = 0x80; //A0-GND A1-GND 4-Bit, 4-Channel, 2-kSPS, ADC ------ PT100 ADC – 0x80 … 0x87. + +uint32_t SensorId_To_SlaveAdd(TEMPERATURE_SENSOR_ID_ENUM SensorId) +{ + switch(SensorId) + { + case TEMP_SENSE_ANALOG_DYEINGH_TEMP1: + case TEMP_SENSE_ANALOG_DYEINGH_TEMP2: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x80; + break; + case TEMP_SENSE_ANALOG_DYEINGH_TEMP3: + case TEMP_SENSE_ANALOG_DYEINGH_TEMP4: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x81; + break; + case TEMP_SENSE_ANALOG_DYEINGH_TEMP5: + //case TEMP_SENSE_ANALOG_DYEINGH_TEMP6: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x82; + break; + /* + case TEMP_SENSE_ANALOG_DYEINGH_TEMP7: + case TEMP_SENSE_ANALOG_DYEINGH_TEMP8: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x83; + break; + case TEMP_SENSE_ANALOG_DYEINGH_TEMP9: + case TEMP_SENSE_ANALOG_DYEINGH_TEMP10: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x84; + break; + case TEMP_SENSE_ANALOG_DYEINGH_TEMP11: + case TEMP_SENSE_ANALOG_DYEINGH_TEMP12: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x85; + break; + case TBD1: + case TBD2: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x86; + break; + case TBD3: + case TBD4: + I2C_ADC_ADS122C04_SLAVE_ADD = 0x87; + break; + */ + default: + break; + } + + return I2C_ADC_ADS122C04_SLAVE_ADD; +} + +uint32_t I2C_Write_SensorId(uint32_t I2C_ID, TEMPERATURE_SENSOR_ID_ENUM SensorId, uint32_t *I2C_Write_buf, uint32_t No_BytesToWrite ) +{ + uint32_t status = OK; + + I2C_ADC_ADS122C04_SLAVE_ADD = SensorId_To_SlaveAdd(SensorId); + status |= I2C_Write(I2C_ID, I2C_ADC_ADS122C04_SLAVE_ADD, I2C_Write_buf, No_BytesToWrite); + + return status; +} + +uint32_t HeadADCPT100_ControlMux_Brfore_Reading(TEMPERATURE_SENSOR_ID_ENUM SensorId) +{ + uint32_t Status = OK; + + uint8_t Write_Buf[2]; + + if(SensorId % 2) + HeadTempSensConfig[SensorId].Reg0.bits.MUX = 0x03; // TBD + else + HeadTempSensConfig[SensorId].Reg0.bits.MUX = 0x04; // TBD + + Write_Buf[0] = ADS122X_WREG_CMD | (ADS122X_CONFIG_0_REG<<2); + Write_Buf[1] = HeadTempSensConfig[SensorId].Reg0.Byte; + + Status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, SensorId, Write_Buf, 1); + + return Status; +} + + +uint32_t I2C_Read_SensorId(uint32_t I2C_ID, TEMPERATURE_SENSOR_ID_ENUM SensorId, uint32_t *I2C_Read_buf, uint32_t No_BytesToRead ) +{ + uint32_t status = OK; + + //HeadADCPT100_ControlMux_Brfore_Reading(SensorId); + //TODO Choose TEMP1 sensor by I/O + I2C_ADC_ADS122C04_SLAVE_ADD = SensorId_To_SlaveAdd(SensorId); + status |= I2C_Read(I2C_ID, I2C_ADC_ADS122C04_SLAVE_ADD + 1, I2C_Read_buf, No_BytesToRead); + + return status; +} + +uint32_t HeadADCPT100_Reset(void) +{ + #ifndef EVALUATION_BOARD + uint32_t status = OK; + uint8_t i; + uint8_t Write_Buf[1]; + + for(i=0;i<MAX_TEMPERATURE_SENSOR_ID; i++) + { + //Reset the device + Write_Buf[0] = ADS122X_RESET_CMD; + //Select_Main_Head_Mux_Channel(); + status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, i, Write_Buf, 1); + //status |= I2C_Write(I2C_ID_HEAD_CARD, I2C_ADC_ADS122C04_SLAVE_ADD, Write_Buf, 1); + //Wait at least (50 us + 32 · t(CLK)) after the RESET command is sent before sending any other command. + + } + #endif + SysCtlDelay(100); // Must delay after hard reset + + return status; +} + + +uint32_t HeadADCPT100_StartSync(TEMPERATURE_SENSOR_ID_ENUM SensorId) +{ + uint32_t Status = OK; + uint8_t Write_Buf[1]; + + if(SensorId > MAX_TEMPERATURE_SENSOR_ID) + Status = ERROR; + + Write_Buf[0] = ADS122X_START_CMD; + + //Select_Main_Head_Mux_Channel(); + + Status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, SensorId, Write_Buf, 1); + //Status |= I2C_Write(I2C_ID_HEAD_CARD, I2C_ADC_ADS122C04_SLAVE_ADD, Write_Buf, 1); + + return Status; +} + +uint32_t HeadADCPT100_PowerDown(TEMPERATURE_SENSOR_ID_ENUM SensorId) +{ + uint32_t Status = OK; + uint8_t Write_Buf[1]; + + if(SensorId > MAX_TEMPERATURE_SENSOR_ID) + Status = ERROR; + + Write_Buf[0] = ADS122X_POWERDOWN_CMD; + + Select_Main_Head_Mux_Channel(); + Status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, SensorId, Write_Buf, 1); + //Status |= I2C_Write(I2C_ID_HEAD_CARD, I2C_ADC_ADS122C04_SLAVE_ADD, Write_Buf, 1); + + return Status; +} + +uint32_t Data_ADC_Head = 0; +uint32_t HeadADCPT100_SendReadDataCommand(TEMPERATURE_SENSOR_ID_ENUM SensorId) +{ + uint32_t Status = OK; + uint8_t Write_Buf[1]; + + uint32_t temp; + + if(SensorId > MAX_TEMPERATURE_SENSOR_ID) + Status = ERROR; + + //Write_Buf[0] = ADS122X_RDATA_CMD; + Write_Buf[0] = ADS122X_RDATA_CMD; + + //Select_Main_Head_Mux_Channel(); + Status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, SensorId, Write_Buf, 1); + //Status |= I2C_Write(I2C_ID_HEAD_CARD, I2C_ADC_ADS122C04_SLAVE_ADD, Write_Buf, 1); + + Status |= I2C_Read_SensorId(I2C_ID_HEAD_CARD, SensorId, &temp, 3); + Data_ADC_Head = (temp & 0xFF0000) >> 16 | (temp & 0xFF00) | (temp & 0x0000FF) << 16;//First send the MSB so we need to reorder the bytes + + CalculateTemperatures(SensorId, Data_ADC_Head); + + + return Status; +} + +uint32_t HeadADCPT100_WriteReg(TEMPERATURE_SENSOR_ID_ENUM SensorId, uint8_t reg, uint8_t writeValue) +{ + uint32_t Status = OK; + uint8_t Write_Buf[2]; + + if(SensorId > MAX_TEMPERATURE_SENSOR_ID) + Status = ERROR; + + Write_Buf[0] = ADS122X_WRITE_CMD(reg); + Write_Buf[1] = writeValue; + + Select_Main_Head_Mux_Channel(); + Status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, SensorId, Write_Buf, 2); + //Status |= I2C_Write(I2C_ID_HEAD_CARD, I2C_ADC_ADS122C04_SLAVE_ADD, Write_Buf, 2); + + return Status; +} + +uint8_t HeadADCPT100_InitConfigReg() +{ + uint8_t i; + + for(i=0;i<MAX_TEMPERATURE_SENSOR_ID;i++) // for now we are using the same configuration to all of them + { + // - - - - - - - - - - Reg0 - - - - - - - - - - + HeadTempSensConfig[i].Reg0.bits.PGA_BYPASS = ADS122X_USE_PGA ;//Bit 0 + HeadTempSensConfig[i].Reg0.bits.GAIN = ADS122X_GAIN_8 ;//Bits 1-3 + HeadTempSensConfig[i].Reg0.bits.MUX = ADS122X_MUX_AIN1_AIN0 ;//Bits 4-7 + + // - - - - - - - - - - Reg1 - - - - - - - - - - + + HeadTempSensConfig[i].Reg1.bits.TS = ADS122X_TEMP_SENSOR_OFF ;//Bit 0 + HeadTempSensConfig[i].Reg1.bits.VREF = ADS122X_VREF_INTERNAL ;//Bits 1-2 + HeadTempSensConfig[i].Reg1.bits.CM = ADS122X_CONVERSION_CONTINUOUS ;//Bit 3 + HeadTempSensConfig[i].Reg1.bits.MODE = ADS122X_OP_MODE_NORMAL ;//Bit 4 + HeadTempSensConfig[i].Reg1.bits.DR = ADS122X_DATA_RATE_20SPS ;//Bits 5-7 + + // - - - - - - - - - - Reg2 - - - - - - - - - - + + HeadTempSensConfig[i].Reg2.bits.IDAC = ADS122X_IDAC_CURRENT_500_UA ;//Bits 0-2 + HeadTempSensConfig[i].Reg2.bits.BCS = ADS122X_BCS_CURRENT_SOURCES_OFF ;//Bit 3 + HeadTempSensConfig[i].Reg2.bits.CRC = ADS122X_CRC_DISABLED ;//BitS 4-5 + HeadTempSensConfig[i].Reg2.bits.DCNT = ADS122X_DCNT_CONVERSION_COUNTER_DISABLED ;//Bit 6 + HeadTempSensConfig[i].Reg2.bits.DRDY = ADS122X_DRDY_NO_NEW_CONVERSION ;//Bit 7 + + // - - - - - - - - - - Reg3 - - - - - - - - - - + HeadTempSensConfig[i].Reg3.bits.Always_write_0 = ADS122X_RESERVED_WRITE_0 ;//BitS 0-1 Always write 0 + HeadTempSensConfig[i].Reg3.bits.I2MUX = ADS122X_IDAC2_DISABLED ;//Bits 2-4 + HeadTempSensConfig[i].Reg3.bits.I1MUX = ADS122X_IDAC1_AIN3 ;//Bits 5-7 + + } + + return OK; +} + + +uint32_t HeadADCPT100_Config_callback(TEMPERATURE_SENSOR_ID_ENUM SensorId, uint32_t Stage) +{ + uint32_t Status = OK; + + #ifndef EVALUATION_BOARD + + uint8_t Write_Buf[2]; + + if (SensorId > MAX_TEMPERATURE_SENSOR_ID) + return ERROR; + + switch(Stage) + { + case SENSOR_CONFIG_REG0: + Write_Buf[0] = ADS122X_WREG_CMD | (ADS122X_CONFIG_0_REG<<2); + Write_Buf[1] = HeadTempSensConfig[SensorId].Reg0.Byte; + break; + case SENSOR_CONFIG_REG1: + Write_Buf[0] = ADS122X_WREG_CMD | (ADS122X_CONFIG_1_REG<<2); + Write_Buf[1] = HeadTempSensConfig[SensorId].Reg1.Byte; + break; + case SENSOR_CONFIG_REG2: + Write_Buf[0] = ADS122X_WREG_CMD | (ADS122X_CONFIG_2_REG<<2); + Write_Buf[1] = HeadTempSensConfig[SensorId].Reg2.Byte; + break; + case SENSOR_CONFIG_REG3: + Write_Buf[0] = ADS122X_WREG_CMD | (ADS122X_CONFIG_3_REG<<2); + Write_Buf[1] = HeadTempSensConfig[SensorId].Reg3.Byte; + break; + default: + Status = ERROR; + } + + Status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, SensorId, Write_Buf, 2); + + #endif + + return Status; +} + +void HeadADCPT100_SensorInitConfig() +{ + int Sensor=0,Register = 0; + + HeadADCPT100_InitConfigReg(); // Initial the configuration registers + + for(Register=0;Register<=SENSOR_CONFIG_REG3;Register++) + { + for(Sensor=0;Sensor<MAX_TEMPERATURE_SENSOR_ID;Sensor++) + { + HeadADCPT100_Config_callback( (TEMPERATURE_SENSOR_ID_ENUM)(Sensor), Register); + } + SysCtlDelay(1000); + } +} + + +uint32_t HeadADCPT100_ReadReg(TEMPERATURE_SENSOR_ID_ENUM SensorId, uint8_t reg, uint8_t *readValue) +{ + uint32_t Status = OK; + + uint8_t Write_Buf[1]; + + Write_Buf[0] = ADS122X_READ_CMD(reg); + + Status |= I2C_Write_SensorId(I2C_ID_HEAD_CARD, SensorId, Write_Buf, 1); + delayUs(1); // delayUs(50); + Status |= I2C_Read_SensorId(I2C_ID_HEAD_CARD, SensorId, readValue, 1); + + return Status; +} + +uint8_t Test_Read_Buf[4] = {0,0,0,0}; + +uint32_t Test_HeadCard_PT100(TEMPERATURE_SENSOR_ID_ENUM SensorId) +{ + uint32_t Status = OK; + uint8_t i = 0; + + #ifdef Test_headCard_With_DispCard_I2C4_Add0xE2_DispID_0 + Select_Main_Head_Mux_Channel_test(); + #else + Select_Main_Head_Mux_Channel(); + #endif + + //HeadADCPT100_Reset(); + HeadADCPT100_InitConfigReg(); + + + HeadADCPT100_Config_callback(SensorId, SENSOR_CONFIG_REG0); + HeadADCPT100_Config_callback(SensorId, SENSOR_CONFIG_REG1); + HeadADCPT100_Config_callback(SensorId, SENSOR_CONFIG_REG2); + HeadADCPT100_Config_callback(SensorId, SENSOR_CONFIG_REG3); + + HeadADCPT100_StartSync(SensorId); + + + + uint8_t Write_Buf[4] = {SENSOR_CONFIG_REG0,SENSOR_CONFIG_REG1,SENSOR_CONFIG_REG2,SENSOR_CONFIG_REG3}; + + for(i=0; i<4; i++) + { + HeadADCPT100_ReadReg(SensorId, Write_Buf[i], &Test_Read_Buf[i]); + + } + + HeadADCPT100_SendReadDataCommand(SensorId); + + + return Status; +} + +uint32_t HeadADCPT100_Calc_Resistance(TEMPERATURE_SENSOR_ID_ENUM SensorId, unsigned int Current_Measurement) +{ + + #define Rref 1650 //ohm + + uint32_t HeadADCPT100_Resistance_100; + + unsigned int Factor_2Rref_E_H; + unsigned int Factor_2Rref_E_L; + + //Resistance = Measurement / (2^23) *4 * Rref / Gain //---------------------- is it *4 ???? + + Factor_2Rref_E_H = 400 * Rref; // 200 to calculate Resistance*100 + + Factor_2Rref_E_L = 8388608 * (2<<(TempSensConfig[SensorId].Reg0.bits.GAIN -1));//2^23*Gain + + HeadADCPT100_Resistance_100 = (float)Current_Measurement / (float)Factor_2Rref_E_L * (float)Factor_2Rref_E_H; + + return HeadADCPT100_Resistance_100; +} diff --git a/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/PT100_ADC.h b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/PT100_ADC.h new file mode 100644 index 000000000..ed204dde5 --- /dev/null +++ b/Software/Embedded_SW/Embedded/Drivers/I2C_Communication/WHS_Card/PT100/PT100_ADC.h @@ -0,0 +1,127 @@ +/* + * PT100_ADC.h + * + * Created on: Jun 30, 2019 + * Author: avi + * update to WHS by Shai 12.11.2019 + */ + +#ifndef DRIVERS_I2C_COMMUNICATION_HEAD_CARD_PT100_PT100_ADC_H_ +#define DRIVERS_I2C_COMMUNICATION_HEAD_CARD_PT100_PT100_ADC_H_ + +extern uint32_t I2C_ADC_ADS122C04_SLAVE_ADD; + +extern uint32_t Data_ADC_Head; + +enum +{ + //16 channels for temperature measuring + HEAD_PT100_ZONE_1_0X80_0, //0 + HEAD_PT100_ZONE_2_0X80_1, //1 + HEAD_PT100_ZONE_3_0X82_0, //2 + HEAD_PT100_ZONE_4_0X82_1, //3 + HEAD_PT100_ZONE_5_0X84_0, //4 + HEAD_PT100_ZONE_6_0X84_1, //5 + HEAD_PT100_ZONE_7_0X86_0, //6 + HEAD_PT100_ZONE_8_0X86_1, //7 + HEAD_PT100_ZONE_9_0X88_0, //8 + HEAD_PT100_ZONE_10_0X88_1, //9 + HEAD_PT100_ZONE_11_0X8A_0, //10 + HEAD_PT100_ZONE_12_0X8A_1, //11 + HEAD_PT100_AIR_HEATER_1_0X8C_0, //12 + HEAD_PT100_AIR_HEATER_2_0X8C_1, //13 + HEAD_PT100_MIXER_0X8E_0, //14 + HEAD_PT100_RESERVE_0X8E_1, //15 +}HEAD_PT100; + +#define HEAD_CONFIG_GAIN ADS122X_GAIN_8 +#define HEAD_CONFIG_IDAC ADS122X_IDAC_CURRENT_1000_UA +#define HEAD_CONFIG_I1MUX ADS122X_IDAC2_AIN0 +#define HEAD_CONFIG_I2MUX ADS122X_IDAC1_AIN3 + +#define HEAD_CONFIG_EVEN_PT100_MUX ADS122X_MUX_AIN0_AIN1 +#define HEAD_CONFIG_ODD_PT100_MUX ADS122X_MUX_AIN3_AIN2 + +#define HEAD_CONFIG_EVEN_PT100_PT_SEL 0X00 +#define HEAD_CONFIG_ODD_PT100_PT_SEL 0X01 + +typedef union +{ + struct + { + unsigned char PGA_BYPASS:1; // + unsigned char GAIN :3; // + unsigned char MUX :4; // + }bits; + unsigned char Byte; +}ADS122C04_CONFIG_REGISTER_0; + +typedef union +{ + struct + { + unsigned char TS :1; // + unsigned char VREF:2; // + unsigned char CM :1; // + unsigned char MODE:1; // + unsigned char DR :3; // + }bits; + unsigned char Byte; +}ADS122C04_CONFIG_REGISTER_1; + +typedef union +{ + struct + { + unsigned char IDAC:3; // + unsigned char BCS :1; // + unsigned char CRC :2; // + unsigned char DCNT:1; // + unsigned char DRDY:1; // + }bits; + unsigned char Byte; +}ADS122C04_CONFIG_REGISTER_2; + +typedef union +{ + struct + { + unsigned char Always_write_0:2; // + unsigned char I2MUX:3; // + unsigned char I1MUX:3; // + }bits; + unsigned char Byte; +}ADS122C04_CONFIG_REGISTER_3; + +typedef struct +{ + ADS122C04_CONFIG_REGISTER_0 Reg0; // + ADS122C04_CONFIG_REGISTER_1 Reg1;// + ADS122C04_CONFIG_REGISTER_2 Reg2; + ADS122C04_CONFIG_REGISTER_3 Reg3; + +}HeadBoardTempSensConfigStruc; + +HeadBoardTempSensConfigStruc HeadTempSensConfig[MAX_TEMPERATURE_SENSOR_ID]; + + +uint32_t SensorId_To_SlaveAdd(TEMPERATURE_SENSOR_ID_ENUM SensorId); +uint32_t I2C_Write_SensorId(uint32_t I2C_ID, TEMPERATURE_SENSOR_ID_ENUM SensorId, uint32_t *I2C_Write_buf, uint32_t No_BytesToWrite ); +uint32_t HeadADCPT100_ControlMux_Brfore_Reading(TEMPERATURE_SENSOR_ID_ENUM SensorId); +uint32_t I2C_Read_SensorId(uint32_t I2C_ID, TEMPERATURE_SENSOR_ID_ENUM SensorId, uint32_t *I2C_Read_buf, uint32_t No_BytesToRead ); +uint32_t HeadADCPT100_Reset(void); +uint32_t HeadADCPT100_StartSync(TEMPERATURE_SENSOR_ID_ENUM SensorId); +uint32_t HeadADCPT100_PowerDown(TEMPERATURE_SENSOR_ID_ENUM SensorId); +uint32_t HeadADCPT100_SendReadDataCommand(TEMPERATURE_SENSOR_ID_ENUM SensorId); +uint32_t HeadADCPT100_WriteReg(TEMPERATURE_SENSOR_ID_ENUM SensorId, uint8_t reg, uint8_t writeValue); +uint8_t HeadADCPT100_InitConfigReg(); +uint32_t HeadADCPT100_Config_callback(TEMPERATURE_SENSOR_ID_ENUM SensorId, uint32_t Stage); +uint32_t HeadADCPT100_ReadReg(TEMPERATURE_SENSOR_ID_ENUM SensorId, uint8_t reg, uint8_t *readValue); +void HeadADCPT100_SensorInitConfig(); +uint32_t HeadADCPT100_Calc_Resistance(TEMPERATURE_SENSOR_ID_ENUM SensorId, unsigned int Current_Measurement); + + + +uint32_t Test_HeadCard_PT100(TEMPERATURE_SENSOR_ID_ENUM SensorId); + +#endif /* DRIVERS_I2C_COMMUNICATION_HEAD_CARD_PT100_PT100_ADC_H_ */ diff --git a/Software/Embedded_SW/Embedded/Modules/AlarmHandling/AlarmHandling.c b/Software/Embedded_SW/Embedded/Modules/AlarmHandling/AlarmHandling.c index 3d230ff5a..44caacc55 100644 --- a/Software/Embedded_SW/Embedded/Modules/AlarmHandling/AlarmHandling.c +++ b/Software/Embedded_SW/Embedded/Modules/AlarmHandling/AlarmHandling.c @@ -232,14 +232,14 @@ AlarmHandlingItemStruc HardCodedAlarmItem[MAX_SYSTEM_ALARMS]={ /* 8014 */ //{eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,6,6,200/*200cc*/,false,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_7_EMPTY}, /* 8015 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,7,7,200/*200cc*/,false,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_8_EMPTY}, -/* 8016 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,0,0,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_1_OVERFLOW}, -/* 8017 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,1,1,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_2_OVERFLOW}, -/* 8018 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,2,2,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_3_OVERFLOW}, -/* 8019 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,3,3,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_4_OVERFLOW}, -/* 8020 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,4,4,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_5_OVERFLOW}, -/* 8021 */ //{eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,5,5,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_6_OVERFLOW}, -/* 8022 */ //{eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,6,6,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_7_OVERFLOW}, -/* 8023 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,7,7,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_8_OVERFLOW}, +/* 8016 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,0,0,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_1_OVERFLOW}, +/* 8017 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,1,1,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_2_OVERFLOW}, +/* 8018 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,2,2,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_3_OVERFLOW}, +/* 8019 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,3,3,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_4_OVERFLOW}, +/* 8020 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,4,4,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_5_OVERFLOW}, +/* 8021 */ //{eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,5,5,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_6_OVERFLOW}, +/* 8022 */ //{eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,6,6,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_7_OVERFLOW}, +/* 8023 */ {eOneSecond,ALARM_SOURCE_TYPE__FluidLevelAlarm,7,7,1800/*1800cc*/,true,DEBUG_LOG_CATEGORY__Error, 0xFF,2,EVENT_TYPE__MID_TANK_8_OVERFLOW}, /* 4000 */ {eOneSecond,ALARM_SOURCE_TYPE__MotorAlarm,HARDWARE_MOTOR_TYPE__MOTO_DRYER_DRIVING,HARDWARE_MOTOR_TYPE__MOTO_DRYER_DRIVING,x_STATUS_OCD,false,DEBUG_LOG_CATEGORY__Error,0xFF,2,EVENT_TYPE__DRYER_MOTOR_OVERCURRENT }, @@ -426,7 +426,11 @@ AlarmHandlingItemStruc HardCodedAlarmItem[MAX_SYSTEM_ALARMS]={ /* 8028 */ {eOneSecond,ALARM_SOURCE_TYPE__DoNotPollAlarm,0,0,0,0,DEBUG_LOG_CATEGORY__Error,0xFF,0,EVENT_TYPE__MID_TANK_5_FILL_TIMEOUT}, /* 8029 */ {eOneSecond,ALARM_SOURCE_TYPE__DoNotPollAlarm,0,0,0,0,DEBUG_LOG_CATEGORY__Error,0xFF,0,EVENT_TYPE__MID_TANK_6_FILL_TIMEOUT}, /* 8030 */ {eOneSecond,ALARM_SOURCE_TYPE__DoNotPollAlarm,0,0,0,0,DEBUG_LOG_CATEGORY__Error,0xFF,0,EVENT_TYPE__MID_TANK_7_FILL_TIMEOUT}, -/* 8031 */ {eOneSecond,ALARM_SOURCE_TYPE__DoNotPollAlarm,0,0,0,0,DEBUG_LOG_CATEGORY__Error,0xFF,0,EVENT_TYPE__MID_TANK_8_FILL_TIMEOUT} +/* 8031 */ {eOneSecond,ALARM_SOURCE_TYPE__DoNotPollAlarm,0,0,0,0,DEBUG_LOG_CATEGORY__Error,0xFF,0,EVENT_TYPE__MID_TANK_8_FILL_TIMEOUT}, + +/* 10002 */ {eOneSecond,ALARM_SOURCE_TYPE__DoNotPollAlarm,0,0,0,0,DEBUG_LOG_CATEGORY__Error,0xFF,0,EVENT_TYPE__NO_WASTE_CARTRIDGE_AVAILABLE}, +/* 10003 */ {eOneSecond,ALARM_SOURCE_TYPE__DoNotPollAlarm,0,0,0,0,DEBUG_LOG_CATEGORY__Error,0xFF,0,EVENT_TYPE__ALL_WASTE_CARTRIDGES_FULL} + }; char AlarmStorePath[30] ="0://SysInfo//Alarm.cfg"; diff --git a/Software/Embedded_SW/Embedded/Modules/General/buttons.c b/Software/Embedded_SW/Embedded/Modules/General/buttons.c index 1b3f16044..6868cfda1 100644 --- a/Software/Embedded_SW/Embedded/Modules/General/buttons.c +++ b/Software/Embedded_SW/Embedded/Modules/General/buttons.c @@ -314,7 +314,7 @@ uint32_t ShortLongOffPB(uint8_t OnOffPB, button *pBtn) if( pBtn->count > SECOND1 ) { pBtn->Action = SHORTPB ; - ReportWithPackageFilter(GeneralFilter,"------------ 2 seconds count PB Power -----------------", __FILE__,__LINE__,0, RpMessage, 0, 0); + ReportWithPackageFilter(GeneralFilter,"------------ 1 seconds count PB Power -----------------", __FILE__,__LINE__,0, RpMessage, 0, 0); } } else @@ -599,7 +599,7 @@ uint32_t LoadStatMachine( button *pBtn) case (REPLONGPB): pBtn->state = sttPRELOAD; pBtn->color = BLINK;*/ - if (ThreadLoadButton( THREAD_LOAD_INIT)) + if (ThreadLoadButton( THREAD_LOAD_INIT) == OK) { pBtn->state = sttPRELOAD ; // to do pBtn->color = colorON; @@ -624,7 +624,7 @@ uint32_t LoadStatMachine( button *pBtn) case (REPLONGPB): pBtn->color = BLUE; Pannel_Leds(THREAD_LOAD, MODE_ON);//AVI+*/ - if (ThreadLoadButton( THREAD_LOAD_INITIAL_TENSION)) + if (ThreadLoadButton( THREAD_LOAD_INITIAL_TENSION) == OK) { pBtn->state = sttRDY ; // to do pBtn->color = colorON; @@ -644,7 +644,7 @@ uint32_t LoadStatMachine( button *pBtn) ReportWithPackageFilter(GeneralFilter,"------------ load.state = sttLOADING -----------------", __FILE__,__LINE__,0, RpMessage, 0, 0); pBtn->color = fastBILNK; Pannel_Leds(THREAD_LOAD, MODE_ON);//AVI+ - if (ThreadLoadButton( THREAD_LOAD_END)) + if (ThreadLoadButton( THREAD_LOAD_END) == OK) { pBtn->state = sttRDY ; // to do pBtn->color = colorON; |