Merge branch 'master' of https://twinetfs.visualstudio.com/Tango/_git/Tango

4 files changed, 106 insertions, 5 deletions

diff --git a/Software/Embedded_SW/Embedded/Common/report/distributor.c b/Software/Embedded_SW/Embedded/Common/report/distributor.c
index a9ebb5c13..35d178712 100644
--- a/Software/Embedded_SW/Embedded/Common/report/distributor.c
+++ b/Software/Embedded_SW/Embedded/Common/report/distributor.c
@@ -590,7 +590,7 @@ STATUS ReportFd(int fd, uint32_t SwitchAddRemove, DistributorHandle Distributor)
  **************************************************************************/
 STATUS ReportFunc(ReportFunction func, uint32_t SwitchAddRemove, DistributorHandle Distributor)
 {
-    int index = 0, i;
+    //int index = 0, i;
 
     /* consistency check: don't add illegal pointer */
     if( func == NULL )
@@ -707,7 +707,7 @@ static void messageDistribute(char *msg,
                               int Severity,
                               int parameter)
 {
-    int index;
+    //int index;
 
     /* pass through the table and send message to destination.
        Assume for consistency: when the destination is fd,
diff --git a/Software/Embedded_SW/Embedded/Drivers/Flash_Memory/Flash_Memory.c b/Software/Embedded_SW/Embedded/Drivers/Flash_Memory/Flash_Memory.c
index 1f7493086..418fde3d3 100644
--- a/Software/Embedded_SW/Embedded/Drivers/Flash_Memory/Flash_Memory.c
+++ b/Software/Embedded_SW/Embedded/Drivers/Flash_Memory/Flash_Memory.c
@@ -371,6 +371,8 @@ int FlashFS_Init()
 
 return 0;
 }
+
+#ifdef EVALUATION_BOARD
 int Init_Ext_Flash()
 {
     uint32_t pui32Dummy[1];
@@ -471,6 +473,104 @@ int Init_Ext_Flash()
 
     return 0;
 }
+#else
+int Init_Ext_Flash()//for the main board
+{
+    uint32_t pui32Dummy[1];
+    uint32_t ui32SysClockFreq;
+
+    //
+    // Set the clocking to run directly from the external crystal/oscillator.
+    // TODO: The SYSCTL_XTAL_ value must be changed to match the value of the
+    // crystal on your board.
+    //
+    ui32SysClockFreq = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
+                                           SYSCTL_OSC_MAIN |
+                                           SYSCTL_USE_PLL |
+                                           SYSCTL_CFG_VCO_480), 120000000);
+
+    // Display the setup on the console.
+    writeLine("SSI3 To DK-TM4C129 FLASH TRANSFER");
+
+    // The SSI3 peripheral must be enabled for use.
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
+
+    //
+    // For this example SSI3 is used with PortF.  The actual port and pins
+    // used may be different on your part, consult the data sheet for more
+    // information.  GPIO port F needs to be enabled so these pins can be used.
+    // TODO: change this to whichever GPIO port you are using.
+    //
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
+
+
+    //
+    // GPIO Port F0 Pin is Locked. So Unlock and write the CR bit
+    //
+    HWREG(GPIO_PORTF_BASE+GPIO_O_LOCK) = GPIO_LOCK_KEY;
+    HWREG(GPIO_PORTF_BASE+GPIO_O_CR)   |= GPIO_PIN_0;
+
+    //
+    // Configure the pin muxing for SSI3 functions on port F
+    //
+    GPIOPinConfigure(GPIO_PF3_SSI3CLK);
+    GPIOPinConfigure(GPIO_PF2_SSI3FSS);
+    GPIOPinConfigure(GPIO_PF1_SSI3XDAT0);
+    GPIOPinConfigure(GPIO_PF0_SSI3XDAT1);
+    GPIOPinConfigure(GPIO_PF4_SSI3XDAT2);
+    GPIOPinConfigure(GPIO_PF5_SSI3XDAT3);
+
+    //
+    // Configure the GPIO settings for the SSI pins.  This function also gives
+    // control of these pins to the SSI hardware.  Consult the data sheet to
+    // see which functions are allocated per pin.
+    // The pins are assigned as follows:
+    //      PF5 - SSI3XDAT3
+    //      PF4 - SSI3XDAT2
+    //      PF0 - SSI3XDAT1
+    //      PF1 - SSI3XDAT0
+    //      PF2 - SSI3Fss
+    //      PF3 - SSI3CLK
+    // TODO: change this to select the port/pin you are using.
+    //
+    GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_1 |
+                   GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5);
+
+    //
+    // Configure and enable the SSI port for SPI master mode.  Use SSI3,
+    // system clock supply, idle clock level low and active low clock in
+    // freescale SPI mode, master mode, 1MHz SSI frequency, and 8-bit data.
+    // For SPI mode, you can set the polarity of the SSI clock when the SSI
+    // unit is idle.  You can also configure what clock edge you want to
+    // capture data on.  Please reference the datasheet for more information on
+    // the different SPI modes.
+    //
+    SSIConfigSetExpClk(SSI3_BASE, ui32SysClockFreq, SSI_FRF_MOTO_MODE_0,
+                       SSI_MODE_MASTER, 1000000, 8);
+
+    //
+    // Enable the SSI3 module.
+    //
+    SSIAdvModeSet(SSI3_BASE,SSI_ADV_MODE_WRITE);
+    SSIAdvFrameHoldEnable(SSI3_BASE);
+    SSIEnable(SSI3_BASE);
+
+    //
+    // Read any residual data from the SSI port.  This makes sure the receive
+    // FIFOs are empty, so we don't read any unwanted junk.  This is done here
+    // because the SPI SSI mode is full-duplex, which allows you to send and
+    // receive at the same time.  The SSIDataGetNonBlocking function returns
+    // "true" when data was returned, and "false" when no data was returned.
+    // The "non-blocking" function checks if there is any data in the receive
+    // FIFO and does not "hang" if there isn't.
+    //
+    while(SSIDataGetNonBlocking(SSI3_BASE, &pui32Dummy[0]))
+    {
+    }
+
+    return 0;
+}
+#endif
 
 int Init_TxBuf(uint32_t NumOfWords, uint32_t* TxBuf)
 {
diff --git a/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h b/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h
index 847677202..fcc53aad1 100644
--- a/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h
+++ b/Software/Embedded_SW/Embedded/Drivers/Peripheral_GPIO/GPIO.h
@@ -172,9 +172,9 @@ typedef enum
 #define ACTIVITY_RED_LED_OFF    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, 0) //Turn OFF Red LED 1
 #define COMM_RED_LED_OFF        ROM_GPIOPinWrite(GPIO_PORTP_BASE, GPIO_PIN_4, 0) //Turn OFF Red LED 2
 
-#define STATUS_GREEN_LED_CHANGE_MODE    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_1, ROM_GPIOPinRead(GPIO_PORTN_BASE, GPIO_PIN_1) ^  1);
-#define ACTIVITY_RED_LED_CHANGE_MODE    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, ROM_GPIOPinRead(GPIO_PORTN_BASE, GPIO_PIN_0) ^  1);
-#define COMM_RED_CHANGE_MODE            ROM_GPIOPinWrite(GPIO_PORTP_BASE, GPIO_PIN_4, ROM_GPIOPinRead(GPIO_PORTP_BASE, GPIO_PIN_4) ^  1);
+#define STATUS_GREEN_LED_CHANGE_MODE    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_1, (ROM_GPIOPinRead(GPIO_PORTN_BASE, GPIO_PIN_1) ^  GPIO_PIN_1));
+#define ACTIVITY_RED_LED_CHANGE_MODE    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, (ROM_GPIOPinRead(GPIO_PORTN_BASE, GPIO_PIN_0) ^  GPIO_PIN_0));
+#define COMM_RED_CHANGE_MODE            ROM_GPIOPinWrite(GPIO_PORTP_BASE, GPIO_PIN_4, (ROM_GPIOPinRead(GPIO_PORTP_BASE, GPIO_PIN_4) ^  GPIO_PIN_4));
 
 typedef void (*GPIOIntCallback)(GPIOInt_t arg);
 
diff --git a/Software/Embedded_SW/Embedded/Drivers/Valves/Valve.c b/Software/Embedded_SW/Embedded/Drivers/Valves/Valve.c
index bae5a5a1c..567366eff 100644
--- a/Software/Embedded_SW/Embedded/Drivers/Valves/Valve.c
+++ b/Software/Embedded_SW/Embedded/Drivers/Valves/Valve.c
@@ -245,6 +245,7 @@ void FPGA_GetAllDispensersValveBusyOCD() // MillisecLoop
 
     ValveRsponse[VALVE_DISPENSER_7].OCD = Valve_Busy_Reg.bits.F2_DISPENSER_VALVE_OCD_7;
     ValveRsponse[VALVE_DISPENSER_7].Busy = Valve_Busy_Reg.bits.Valve_busy_6;
+
     ValveRsponse[VALVE_DISPENSER_8].OCD = Valve_Busy_Reg.bits.F2_DISPENSER_VALVE_OCD_8;
     ValveRsponse[VALVE_DISPENSER_8].Busy = Valve_Busy_Reg.bits.Valve_busy_7;
 }