From 3f6ff04da7c8c3fb2d41ee0d5f355d9bd449492a Mon Sep 17 00:00:00 2001 From: Shlomo Hecht Date: Tue, 15 May 2018 13:00:27 +0300 Subject: FPGA beautifying. some control improvements --- Software/Embedded_SW/Embedded/Modules/Control/control.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Software/Embedded_SW/Embedded/Modules/Control/control.c') diff --git a/Software/Embedded_SW/Embedded/Modules/Control/control.c b/Software/Embedded_SW/Embedded/Modules/Control/control.c index 08001cf01..40eee95c8 100644 --- a/Software/Embedded_SW/Embedded/Modules/Control/control.c +++ b/Software/Embedded_SW/Embedded/Modules/Control/control.c @@ -90,7 +90,7 @@ int ControlPhaseDelay = 300; //the control task enters only after data gathering Mailbox_Handle ControlMsgQ = NULL; bool ControlRestart; static GateMutex_Handle gateControlDB; - +Task_Handle Control_Task_Handle; ControlDeviceStruc ControlArray[MAX_TANGO_CONTROL_DEVICES]; uint32_t ControlDatalog[MAX_TANGO_CONTROL_DEVICES]; uint32_t Control_timerBase = TIMER0_BASE; //Timer handle @@ -321,7 +321,7 @@ void controlTask(UArg arg0, UArg arg1) //uint16_t length; //Clock_setTimeout(HostKAClock, 1000); //Clock_start(HostKAClock); - + Control_Task_Handle = Task_self(); while(1) { -- cgit v1.3.1