From 82dcbadca6ed35aee61bb5f9f8f364414f7427f3 Mon Sep 17 00:00:00 2001 From: Avi Levkovich Date: Tue, 10 Jul 2018 12:20:50 +0300 Subject: Add the functions: Power_Off, Power_Reset, Control_WD and Read_Fans_Tacho --- Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c | 42 ++++++++++++++++++++++ Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h | 2 +- .../Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h | 3 ++ .../Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c | 37 +++++++++++++++++++ .../Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h | 3 ++ 5 files changed, 86 insertions(+), 1 deletion(-) (limited to 'Software/Embedded_SW/Embedded') diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c index 3cd4c8f0d..26b1dbae7 100644 --- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c +++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.c @@ -176,6 +176,48 @@ void FPGA_Init() //} +uint32_t Read_Fans_Tacho()//TODO.... not all of them connected yet, and some don't have tacho... +{ + uint32_t Status = 0; + static unsigned short Counters[9]; + + if( Counters[0] == F1_Tacho_reg0) // The big Fan in the drawer + Status|= (0x01<<0); + Counters[0] = F1_Tacho_reg0; + + if( Counters[1] == F1_Tacho_reg1); // Small Fan in the drawer + Status|= (0x01<<1); + Counters[1] = F1_Tacho_reg1; + + if( Counters[2] == F1_Tacho_reg2); // Small Fan in the drawer + Status|=(0x01<<2); + Counters[2] = F1_Tacho_reg2; + + if( Counters[3] == F1_Tacho_reg3); // Small Fan in the drawer + Status|= (0x01<<3); + Counters[3] = F1_Tacho_reg3; + + if( Counters[4] == F1_Tacho_reg4); // Small Fan in the drawer + Status|= (0x01<<4); + Counters[4] = F1_Tacho_reg4; + if( Counters[5] == F1_Tacho_reg5); + Status|= (0x01<<5); + Counters[5] = F1_Tacho_reg5; + + if( Counters[6] == F1_Tacho_reg6); + Status|= (0x01<<6); + Counters[6] = F1_Tacho_reg6; + + if( Counters[7] == F1_Tacho_reg7); + Status|= (0x01<<7); + Counters[7] = F1_Tacho_reg7; + + if( Counters[8] = F2_Tacho_reg0); + Status|= (0x01<<8); + Counters[8] = F2_Tacho_reg0; + + return Status; +} diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h index 531eae734..f5a734a36 100644 --- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h +++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA.h @@ -6,6 +6,6 @@ int FPGA_Test_ReadBack(unsigned char FPGA_NUM, unsigned short Value, unsigned sh int FPGA_ReadVersion(unsigned char FPGA_NUM, unsigned char *Version, unsigned char *Year, unsigned char *Month, unsigned char *Day); void FPGA_Init(); //void FPGA_Read_limit_Switches(void); - +uint32_t Read_Fans_Tacho(); #endif //FPGA_H diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h index ffd484d65..f634c3348 100644 --- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h +++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_Comm.h @@ -357,6 +357,9 @@ #define F2_Prescaler1_reg12 (*((volatile short *)(FPGA2_BASE | 0x122))) //Variable for prescaler divisions -amount of prescaled clocks clk input of prescaler of signal VALVE registers. 16bits #define F2_Prescaler1_reg13 (*((volatile short *)(FPGA2_BASE | 0x132))) //Variable for prescaler divisions -amount of prescaled clocks clk input of prescaler of signal debouncer of the limit switch. 14bits +//Watchdog +#define F2_Watchdog_reg (*((volatile short *)(FPGA2_BASE | 0x140)))//Watchdog enable bit, watchdog value + //SSI #define F2_DISPENSER_ROTENC_DATA_p_1_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x180))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_1_RX_msb (*((volatile short *)(FPGA2_BASE | 0x182))) //16 bit MSB if nessesary diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c index 987978e00..104b1d719 100644 --- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c +++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.c @@ -179,6 +179,43 @@ uint32_t DeActivateDilutorPump() F2_CTRL &= ~CHILLER_SSR9_CTRL; return OK; } +//---------------------------------- + +void Power_Off()//Power Down +{ + F2_CTRL |= PDOWN_RL1_CTRL; +} + +void Power_Reset()// Resets the MCU +{ + F3_SW_RESET_reg &= ~BIT0; + SysCtlDelay(1000); + F3_SW_RESET_reg |= BIT0; +} + + +uint32_t Control_WD(bool IsEnable, unsigned char SetTimer_Steps100mSec) // Control_WD(ENABLE, 30);//Enable the watchdog for 3 seconds +/* + * To enable the watchdog write '1' to bit No. 14 (value 0x40). + * To set the watchdog time, write to lower 8 bits of the register number of times to count with a step of 0.1 seconds. + * For example, for 3 seconds write the number 30 (0x1E). + * If you will write the 0x4000 the watchdog will be enabled and activated immediately, the control register will be resetted. + * If you will write the 0x40xx, where 0xFF >= xx > 0, the watchdog will be enabled, will start count the specified time, + * the control register will take the value it had before to be resetted. + */ +{ + if (IsEnable == DISABLE) + { + F2_Watchdog_reg = 0; + } + else + { + F2_Watchdog_reg = 0x40 | SetTimer_Steps100mSec; // Enable the watchdog + } + return OK; +} + + diff --git a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h index f0210e9c5..48d7171a5 100644 --- a/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h +++ b/Software/Embedded_SW/Embedded/Drivers/FPGA/FPGA_GPIO/FPGA_GPIO.h @@ -182,5 +182,8 @@ void FPGA_Read_limit_Switches_Registers(); uint32_t ActivateDilutorPump(); uint32_t DeActivateDilutorPump(); +void Power_Off(); +void Power_Reset(); +uint32_t Control_WD(bool IsEnable, unsigned char SetTimer_Steps100mSec); #endif /* DRIVERS_FPGA_FPGA_GPIO_FPGA_GPIO_H_ */ -- cgit v1.3.1