/* * FPGA_Comm.h * * Uptaded: May 09, 2018 * By: Avi * * Based on: * Tango_HW_SW.xlsx * Version: 3 * 08/05/2018 */ #ifndef DRIVERS_FPGA_FPGA_COMM_H_ #define DRIVERS_FPGA_FPGA_COMM_H_ #include //Address is = 16 Bit : 4bit_base , 3bit_fpga_base , 9bit_Address(Byte) //Base Address 0X000 #include "inc/hw_memmap.h" //#define BASE 0x60000000 //0x60000000 | (0x00 << 12) #define FPGA1_BASE 0x60000000//(BASE | (0x00 << 0x09)) #define FPGA2_BASE 0x60000400//(BASE | (0x02 << 0x09)) #define FPGA3_BASE 0x60000800//(BASE | (0x04 << 0x09)) //Registers definitions // * * * * * * * * * * * * * * * * FPGA 1 * * * * * * * * * * * * * * * * // //Version1 #define F1_Ver1_D (*((volatile short *)(FPGA1_BASE | 0x000))) //Version of Fpga is held here //Version2 #define F1_Ver2_D (*((volatile short *)(FPGA1_BASE | 0x010))) //Version of Fpga is held here //GPI shorterrupt LS_01 Registers #define F1_GPI_LS1_D (*((volatile short *)(FPGA1_BASE | 0x020))) //Reads the direct values that are currently being sent to the fpga. #define F1_GPI_LS1_L (*((volatile short *)(FPGA1_BASE | 0x022))) //Value of the latched shorterrupts that have occurred #define F1_GPI_LS1_M (*((volatile short *)(FPGA1_BASE | 0x024))) //Value of the shorterrupt mask, Default is 0x0000 //GPI shorterrupt LS_02 Registers #define F1_GPI_LS2_D (*((volatile short *)(FPGA1_BASE | 0x030))) //Reads the direct values that are currently being sent to the fpga. #define F1_GPI_LS2_L (*((volatile short *)(FPGA1_BASE | 0x032))) //Value of the latched shorterrupts that have occurred #define F1_GPI_LS2_M (*((volatile short *)(FPGA1_BASE | 0x034))) //Value of the shorterrupt mask, Default is 0x0000 //GPI shorterrupt LS_03 Registers #define F1_GPI_LS3_D (*((volatile short *)(FPGA1_BASE | 0x040))) //Reads the direct values that are currently being sent to the fpga. #define F1_GPI_LS3_L (*((volatile short *)(FPGA1_BASE | 0x042))) //Value of the latched shorterrupts that have occurred #define F1_GPI_LS3_M (*((volatile short *)(FPGA1_BASE | 0x044))) //Value of the shorterrupt mask, Default is 0x0000 //Moto_Driver_NBUSY_register1 #define F1_Moto_Driver_NBUSY1_D (*((volatile short *)(FPGA1_BASE | 0x050))) //Reads the direct values that are currently being sent to the fpga. #define F1_Moto_Driver_NBUSY1_L (*((volatile short *)(FPGA1_BASE | 0x052))) //Value of the latched shorterrupts that have occurred #define F1_Moto_Driver_NBUSY1_M (*((volatile short *)(FPGA1_BASE | 0x054))) //Value of the shorterrupt mask, Default is 0x0000 //Moto_Driver_NBUSY_register2 #define F1_Moto_Driver_NBUSY2_D (*((volatile short *)(FPGA1_BASE | 0x060))) //Reads the direct values that are currently being sent to the fpga. #define F1_Moto_Driver_NBUSY2_L (*((volatile short *)(FPGA1_BASE | 0x062))) //Value of the latched shorterrupts that have occurred #define F1_Moto_Driver_NBUSY2_M (*((volatile short *)(FPGA1_BASE | 0x064))) //Value of the shorterrupt mask, Default is 0x0000 //GPI_EXTWINDER_and_TFEED_BRK #define F1_GPI_EXTWINDER_D (*((volatile short *)(FPGA1_BASE | 0x070))) //Reads the direct values that are currently being sent to the fpga. #define F1_GPI_EXTWINDER_L (*((volatile short *)(FPGA1_BASE | 0x072))) //Value of the latched shorterrupts that have occurred #define F1_GPI_EXTWINDER_M (*((volatile short *)(FPGA1_BASE | 0x074))) //Value of the shorterrupt mask, Default is 0x0000 //SPI_Busy_register1 #define F1_SPI_Busy1_D (*((volatile short *)(FPGA1_BASE | 0x090))) //Reads the direct values that are currently being sent to the fpga. #define F1_SPI_Busy1_L (*((volatile short *)(FPGA1_BASE | 0x092))) //Value of the latched shorterrupts that have occurred #define F1_SPI_Busy1_M (*((volatile short *)(FPGA1_BASE | 0x094))) //Value of the shorterrupt mask, Default is 0x0000 //SPI_Busy_register2 #define F1_SPI_Busy2_D (*((volatile short *)(FPGA1_BASE | 0x0A0))) //Reads the direct values that are currently being sent to the fpga. #define F1_SPI_Busy2_L (*((volatile short *)(FPGA1_BASE | 0x0A2))) //Value of the latched shorterrupts that have occurred #define F1_SPI_Busy2_M (*((volatile short *)(FPGA1_BASE | 0x0A4))) //Value of the shorterrupt mask, Default is 0x0000 //Moto_Driver_NSTBYRST_register1 #define F1_Moto_Driver_NSTBYRST1 (*((volatile short *)(FPGA1_BASE | 0x0B2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //Moto_Driver_NSTBYRST_register2 #define F1_Moto_Driver_NSTBYRST2 (*((volatile short *)(FPGA1_BASE | 0x0C2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //Moto_Driver_SW_register1 #define F1_Moto_Driver_SW1 (*((volatile short *)(FPGA1_BASE | 0x0D2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //Moto_Driver_SW_register2 #define F1_Moto_Driver_SW2 (*((volatile short *)(FPGA1_BASE | 0x0E2))) //Writes to values. Readback thevaluessthat are currently in the GPO register #define F1_Prescaler1_reg9 (*((volatile short *)(FPGA1_BASE | 0x0F2 ))) //Parameter for prescaler divisions //QEI_SCREW_ROTENC #define F1_SCREW_ROTENC_L (*((volatile short *)(FPGA1_BASE | 0x100))) //Value of the lsb of the QEI register #define F1_SCREW_ROTENC_M (*((volatile short *)(FPGA1_BASE | 0x102))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F1_SCREW_ROTENC_I (*((volatile short *)(FPGA1_BASE | 0x104))) //value of index counter //QEI_RSPARE_ROTENC #define F1_RSPARE_ROTENC_L (*((volatile short *)(FPGA1_BASE | 0x110))) //Value of the lsb of the QEI register #define F1_RSPARE_ROTENC_M (*((volatile short *)(FPGA1_BASE | 0x112))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F1_RSPARE_ROTENC_I (*((volatile short *)(FPGA1_BASE | 0x114))) //value of index counter //QEI_LSPARE1_ROTENC #define F1_LSPARE1_ROTENC_L (*((volatile short *)(FPGA1_BASE | 0x120))) //Value of the lsb of the QEI register #define F1_LSPARE1_ROTENC_M (*((volatile short *)(FPGA1_BASE | 0x122))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F1_LSPARE1_ROTENC_I (*((volatile short *)(FPGA1_BASE | 0x124))) //value of index counter //QEI_RSPEEDSENS_ROTENC #define F1_RSPEEDSENS_ROTENC_L (*((volatile short *)(FPGA1_BASE | 0x130))) //Value of the lsb of the QEI register #define F1_RSPEEDSENS_ROTENC_M (*((volatile short *)(FPGA1_BASE | 0x132))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F1_RSPEEDSENS_ROTENC_I (*((volatile short *)(FPGA1_BASE | 0x134))) //value of index counter //QEI_LSPARE2_ROTENC #define F1_LSPARE2_ROTENC_L (*((volatile short *)(FPGA1_BASE | 0x140))) //Value of the lsb of the QEI register #define F1_LSPARE2_ROTENC_M (*((volatile short *)(FPGA1_BASE | 0x142))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F1_LSPARE2_ROTENC_I (*((volatile short *)(FPGA1_BASE | 0x144))) //value of index counter //QEI_DRYER_LOADARM_ROTENC #define F1_DRYER_LOADARM_ROTENC_L (*((volatile short *)(FPGA1_BASE | 0x150))) //Value of the lsb of the QEI register #define F1_DRYER_LOADARM_ROTENC_M (*((volatile short *)(FPGA1_BASE | 0x152))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F1_DRYER_LOADARM_ROTENC_I (*((volatile short *)(FPGA1_BASE | 0x154))) //value of index counter //WATCHDOG #define F1_Watchdog_reg (*((volatile short *)(FPGA1_BASE | 0x160)))//Watchdog enable bit, watchdog value - F1_gpo_01 BIT2 DYEINGH_SSR10_CTRL HeadHeaterZ5 //4 Small drawer Fans #define F1_gpi_FANS (*((volatile short *)(FPGA1_BASE | 0x170)))//FANs on/off indication bits //SSI #define F1_RSPARE_ROTENC_DATA_p_RX_lsb (*((volatile short *)(FPGA1_BASE | 0x180))) //The 16 Lsb bits of the shifted in data. #define F1_RSPARE_ROTENC_DATA_p_RX_msb (*((volatile short *)(FPGA1_BASE | 0x182))) //16 bit MSB if nessesary #define F1_RSPARE_ROTENC_DATA_p_TX (*((volatile short *)(FPGA1_BASE | 0x18E))) //This register triggers a TX transmission #define F1_LSPARE_ROTENC_DATA_p_RX_lsb (*((volatile short *)(FPGA1_BASE | 0x190))) //The 16 Lsb bits of the shifted in data. #define F1_LSPARE_ROTENC_DATA_p_RX_msb (*((volatile short *)(FPGA1_BASE | 0x192))) //16 bit MSB if nessesary #define F1_LSPARE_ROTENC_DATA_p_TX (*((volatile short *)(FPGA1_BASE | 0x19E))) //This register triggers a TX transmission #define F1_RDANCER_ROTENC_DATA_p_RX_lsb (*((volatile short *)(FPGA1_BASE | 0x1A0))) //The 16 Lsb bits of the shifted in data. #define F1_RDANCER_ROTENC_DATA_p_RX_msb (*((volatile short *)(FPGA1_BASE | 0x1A2))) //16 bit MSB if nessesary #define F1_RDANCER_ROTENC_DATA_p_TX (*((volatile short *)(FPGA1_BASE | 0x1AE))) //This register triggers a TX transmission #define F1_LDANCER2_ROTENC_DATA_p_RX_lsb (*((volatile short *)(FPGA1_BASE | 0x1B0))) //The 16 Lsb bits of the shifted in data. #define F1_LDANCER2_ROTENC_DATA_p_RX_msb (*((volatile short *)(FPGA1_BASE | 0x1B2))) //16 bit MSB if nessesary #define F1_LDANCER2_ROTENC_DATA_p_TX (*((volatile short *)(FPGA1_BASE | 0x1BE))) //This register triggers a TX transmission #define F1_LDANCER1_ROTENC_DATA_p_RX_lsb (*((volatile short *)(FPGA1_BASE | 0x1C0))) //The 16 Lsb bits of the shifted in data. #define F1_LDANCER1_ROTENC_DATA_p_RX_msb (*((volatile short *)(FPGA1_BASE | 0x1C2))) //16 bit MSB if nessesary #define F1_LDANCER1_ROTENC_DATA_p_TX (*((volatile short *)(FPGA1_BASE | 0x1CE))) //This register triggers a TX transmission //FPGA VER 050219 #define F1_GPO_02_bus (*((volatile short *)(FPGA1_BASE | 0x1D0))) //General purpose GPIO register #define F1_Tacho_reg8 (*((volatile short *)(FPGA1_BASE | 0x1E0))) //This Register stores the Tacho counter #define F1_Tacho_reg9 (*((volatile short *)(FPGA1_BASE | 0x1E2))) //This Register stores the Tacho counter A to A // //SPI_MOTO_RLOADING_A1 #define F1_MOTO_RLOADING_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x200))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RLOADING_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x202))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RLOADING_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x204))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_RLOADING_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x206))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_RLOADING_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x208))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_RDRIVING_A1 #define F1_MOTO_RDRIVING_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x210))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RDRIVING_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x212))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RDRIVING_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x214))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_RDRIVING_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x216))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_RDRIVING_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x218))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_LDRIVING_A1 #define F1_MOTO_LDRIVING_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x220))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LDRIVING_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x222))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LDRIVING_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x224))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_LDRIVING_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x226))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_LDRIVING_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x228))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_LLOADING_A1 #define F1_MOTO_LLOADING_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x230))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LLOADING_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x232))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LLOADING_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x234))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_LLOADING_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x236))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_LLOADING_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x238))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_DRYER_LOADARM_A1 #define F1_MOTO_DRYER_LOADARM_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x240))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DRYER_LOADARM_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x242))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DRYER_LOADARM_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x244))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_DRYER_LOADARM_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x246))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_DRYER_LOADARM_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x248))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_DRYER_DRIVING_A1 #define F1_MOTO_DRYER_DRIVING_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x250))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DRYER_DRIVING_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x252))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DRYER_DRIVING_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x254))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_DRYER_DRIVING_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x256))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_DRYER_DRIVING_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x258))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_DH_CLEANHEAD_A1 #define F1_MOTO_DH_CLEANHEAD_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x260))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DH_CLEANHEAD_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x262))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DH_CLEANHEAD_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x264))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_DH_CLEANHEAD_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x266))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_DH_CLEANHEAD_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x268))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_DH_CLEANMECH_A1 #define F1_MOTO_DH_CLEANMECH_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x270))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DH_CLEANMECH_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x272))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DH_CLEANMECH_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x274))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_DH_CLEANMECH_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x276))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_DH_CLEANMECH_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x278))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_SCREW_A1 #define F1_MOTO_SCREW_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x280))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_SCREW_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x282))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_SCREW_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x284))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_SCREW_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x286))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_SCREW_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x288))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_WINDER_A1 #define F1_MOTO_WINDER_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x290))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_WINDER_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x292))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_WINDER_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x294))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_WINDER_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x296))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_WINDER_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x298))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_RLOADARM_A1 #define F1_MOTO_RLOADARM_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x2A0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RLOADARM_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x2A2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RLOADARM_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x2A4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_RLOADARM_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x2A6))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_RLOADARM_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x2A8))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_RDANCER_A1 #define F1_MOTO_RDANCER_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x2B0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RDANCER_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x2B2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_RDANCER_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x2B4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_RDANCER_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x2B6))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_RDANCER_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x2B8))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_LDANCER1_A1 #define F1_MOTO_LDANCER1_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x2C0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LDANCER1_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x2C2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LDANCER1_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x2C4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_LDANCER1_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x2C6))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_LDANCER1_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x2C8))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_LDANCER2_A1 #define F1_MOTO_LDANCER2_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x2D0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LDANCER2_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x2D2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LDANCER2_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x2D4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_LDANCER2_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x2D6))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_LDANCER2_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x2D8))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_DRYER_LID_A1 #define F1_MOTO_DRYER_LID_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x2E0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DRYER_LID_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x2E2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DRYER_LID_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x2E4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_DRYER_LID_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x2E6))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_DRYER_LID_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x2E8))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_DH_LID_A1 #define F1_MOTO_DH_LID_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x2F0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DH_LID_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x2F2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_DH_LID_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x2F4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_DH_LID_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x2F6))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_DH_LID_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x2F8))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_LPIVOT1_A1 #define F1_MOTO_LPIVOT1_A1_TX_00 (*((volatile short *)(FPGA1_BASE | 0x300))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LPIVOT1_A1_TX_01 (*((volatile short *)(FPGA1_BASE | 0x302))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F1_MOTO_LPIVOT1_A1_RX_00 (*((volatile short *)(FPGA1_BASE | 0x304))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F1_MOTO_LPIVOT1_A1_RX_01 (*((volatile short *)(FPGA1_BASE | 0x306))) //The 16 Lsb bits of the shifted in data. #define F1_MOTO_LPIVOT1_A1_WORDS (*((volatile short *)(FPGA1_BASE | 0x308))) //The amount of spi words (usually byte sized) per transmission. #define F1_Moto_Driver_SPI_DIRECTION1 (*((volatile short *)(FPGA1_BASE | 0x380))) // #define F1_Moto_Driver_SPI_DIRECTION2 (*((volatile short *)(FPGA1_BASE | 0x390))) // //FPGA VER 050219 #define F1_gpo_cnt_A_reg (*((volatile short *)(FPGA1_BASE | 0x3B0))) //This Register stores the costumer Tacho counter A to A ( F1_gpo_cnt_A_reg must be greater than 1 => F1_gpo_cnt_A_reg>=1) #define F1_Tacho_reg0 (*((volatile short *)(FPGA1_BASE | 0x3C0))) //This Register stores the Tacho counter #define F1_Tacho_reg1 (*((volatile short *)(FPGA1_BASE | 0x3C2))) //This Register stores the Tacho counter #define F1_Tacho_reg2 (*((volatile short *)(FPGA1_BASE | 0x3C4))) //This Register stores the Tacho counter #define F1_Tacho_reg3 (*((volatile short *)(FPGA1_BASE | 0x3C6))) //This Register stores the Tacho counter #define F1_Tacho_reg4 (*((volatile short *)(FPGA1_BASE | 0x3C8))) //This Register stores the Tacho counter #define F1_Tacho_reg5 (*((volatile short *)(FPGA1_BASE | 0x3CA))) //This Register stores the Tacho counter #define F1_Tacho_reg6 (*((volatile short *)(FPGA1_BASE | 0x3CC))) //This Register stores the Tacho counter #define F1_Tacho_reg7 (*((volatile short *)(FPGA1_BASE | 0x3CE))) //This Register stores the Tacho counter //read SSR10 #define F1_CTRL_bus1_reg (*((volatile short *)(FPGA1_BASE | 0x3A0))) //This Register stores the ssr with n_heater_wd_expire value - read of the value of F1_GPO_DILUTORPUMP_SSR10_CTRL //GPO #define F1_gpo_01 (*((volatile short *)(FPGA1_BASE | 0x3D2))) //Gpo Register Miscellaneous output register, 16bits //Prescaler #define F1_Prescaler1_reg1 (*((volatile short *)(FPGA1_BASE | 0x3E0))) //Parameter for prescaler divisions - 6bit ssi high duty cycle value for prescaler #define F1_Prescaler1_reg2 (*((volatile short *)(FPGA1_BASE | 0x3E2))) //Parameter for prescaler divisions - 6bit ssi low duty cycle value for prescaler #define F1_Prescaler1_reg3 (*((volatile short *)(FPGA1_BASE | 0x3E4))) //Parameter for prescaler divisions - 3bit spi moto low duty cycle value for pmw #define F1_Prescaler1_reg4 (*((volatile short *)(FPGA1_BASE | 0x3E6))) //Parameter for prescaler divisions - 3bit spi moto high duty cycle value for pmw #define F1_Prescaler1_reg5 (*((volatile short *)(FPGA1_BASE | 0x3E8))) //Parameter for prescaler divisions - Parameter for prescaler divisions -amount of prescaled clocks for counter of signal All Tachos. ####8_Bit##### #define F1_Prescaler1_reg6 (*((volatile short *)(FPGA1_BASE | 0x3EA))) //pre scaler for tacho A_To_A #define F1_Prescaler1_reg7 (*((volatile short *)(FPGA1_BASE | 0x3EC))) //Parameter for prescaler divisions #define F1_Prescaler1_reg8 (*((volatile short *)(FPGA1_BASE | 0x3EE))) //Parameter for prescaler divisions //Test #define F1_Test (*((volatile short *)(FPGA1_BASE | 0x3F0))) //Readback not -gives the inverse of the written to value // * * * * * * * * * * * * * * * * FPGA 2 * * * * * * * * * * * * * * * * // //Version1 #define F2_Ver1_D (*((volatile short *)(FPGA2_BASE | 0x000))) //Version of Fpga is held here //Version2 #define F2_Ver2_D (*((volatile short *)(FPGA2_BASE | 0x010))) //Version of Fpga is held here //GPI shorterrupt LS_01 Registers #define F2_LS_01_Direct (*((volatile short *)(FPGA2_BASE | 0x020))) //Reads the direct values that are currently being sent to the fpga. #define F2_LS_01_Latched (*((volatile short *)(FPGA2_BASE | 0x022))) //Value of the latched shorterrupts that have occurred #define F2_LS_01_Mask (*((volatile short *)(FPGA2_BASE | 0x024))) //Value of the shorterrupt mask, Default is 0x0000 //GPI shorterrupt LS_02 Registers #define F2_LS_02_Direct (*((volatile short *)(FPGA2_BASE | 0x030))) //Reads the direct values that are currently being sent to the fpga. #define F2_LS_02_Latched (*((volatile short *)(FPGA2_BASE | 0x032))) //Value of the latched shorterrupts that have occurred #define F2_LS_02_Mask (*((volatile short *)(FPGA2_BASE | 0x034))) //Value of the shorterrupt mask, Default is 0x0000 //GPI shorterrupt LS_03 Registers #define F2_LS_03_Direct (*((volatile short *)(FPGA2_BASE | 0x040))) //Reads the direct values that are currently being sent to the fpga. #define F2_LS_03_Latched (*((volatile short *)(FPGA2_BASE | 0x042))) //Value of the latched shorterrupts that have occurred #define F2_LS_03_Mask (*((volatile short *)(FPGA2_BASE | 0x044))) //Value of the shorterrupt mask, Default is 0x0000 //Moto_Driver_NBUSY_register1 #define F2_Moto_Driver_NBUSY1_D (*((volatile short *)(FPGA2_BASE | 0x050))) //Reads the direct values that are currently being sent to the fpga. #define F2_Moto_Driver_NBUSY1_L (*((volatile short *)(FPGA2_BASE | 0x052))) //Value of the latched shorterrupts that have occurred #define F2_Moto_Driver_NBUSY1_M (*((volatile short *)(FPGA2_BASE | 0x054))) //Value of the shorterrupt mask, Default is 0x0000 //DISPENSER_VALVE_IN #define F2_DISPENSER_VALVE_IN_Direct (*((volatile short *)(FPGA2_BASE | 0x060))) //Reads the direct values that are currently being sent to the fpga. #define F2_DISPENSER_VALVE_IN_Latched (*((volatile short *)(FPGA2_BASE | 0x062))) //Value of the latched shorterrupts that have occurred #define F2_DISPENSER_VALVE_IN_Mask (*((volatile short *)(FPGA2_BASE | 0x064))) //Value of the shorterrupt mask, Default is 0x0000 //GPI_REGISTER1 #define F2_GPI_REGISTER1_Direct (*((volatile short *)(FPGA2_BASE | 0x070))) //Reads the direct values that are currently being sent to the fpga. #define F2_GPI_REGISTER1_Latched (*((volatile short *)(FPGA2_BASE | 0x072))) //Value of the latched shorterrupts that have occurred #define F2_GPI_REGISTER1_Mask (*((volatile short *)(FPGA2_BASE | 0x074))) //Value of the shorterrupt mask, Default is 0x0000 //LS_04 #define F2_LS_04_Direct (*((volatile short *)(FPGA2_BASE | 0x080))) //Version of Fpga is held here #define F2_LS_04_Latched (*((volatile short *)(FPGA2_BASE | 0x082))) //Value of the latched shorterrupts that have occurred #define F2_LS_04_Mask (*((volatile short *)(FPGA2_BASE | 0x084))) //Value of the shorterrupt mask, Default is 0x0000 //SPI_Busy_register1 #define F2_SPI_Busy1_D (*((volatile short *)(FPGA2_BASE | 0x090))) //Reads the direct values that are currently being sent to the fpga. #define F2_SPI_Busy1_L (*((volatile short *)(FPGA2_BASE | 0x092))) //Value of the latched shorterrupts that have occurred #define F2_SPI_Busy1_M (*((volatile short *)(FPGA2_BASE | 0x094))) //Value of the shorterrupt mask, Default is 0x0000 //SPI_Busy_register2 #define F2_SPI_Busy2_D (*((volatile short *)(FPGA2_BASE | 0x0A0))) //Reads the direct values that are currently being sent to the fpga. #define F2_SPI_Busy2_L (*((volatile short *)(FPGA2_BASE | 0x0A2))) //Value of the latched shorterrupts that have occurred #define F2_SPI_Busy2_M (*((volatile short *)(FPGA2_BASE | 0x0A4))) //Value of the shorterrupt mask, Default is 0x0000 //Moto_Driver_NSTBYRST_register1 #define F2_Moto_Driver_NSTBYRST1 (*((volatile short *)(FPGA2_BASE | 0x0B2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //DISPENSER_VALVE_OUT #define F2_DISPENSER_VALVE_OUT (*((volatile short *)(FPGA2_BASE | 0x0C2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //Moto_Driver_SW_register1 #define F2_Moto_Driver_SW1 (*((volatile short *)(FPGA2_BASE | 0x0D2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //CTRL #define F2_CTRL (*((volatile short *)(FPGA2_BASE | 0x0E2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //GPO_REGISTER #define F2_GPO_REGISTER (*((volatile short *)(FPGA2_BASE | 0x0F2))) //Writes to values. Readback thevaluessthat are currently in the GPO register #define F2_Prescaler1_reg10 (*((volatile short *)(FPGA2_BASE | 0x102))) //Variable for prescaler divisions -amount of prescaled clocks for counter of signal Blower Tacho. 8 bits #define F2_Prescaler1_reg11 (*((volatile short *)(FPGA2_BASE | 0x112))) //Parameter for prescaler divisions -amount of prescaled clocks clk input of pwm of signal F2_GPO_BLOWER_PWM. 8bits #define F2_Prescaler1_reg12 (*((volatile short *)(FPGA2_BASE | 0x122))) //Variable for prescaler divisions -amount of prescaled clocks clk input of prescaler of signal VALVE registers. 16bits #define F2_Prescaler1_reg13 (*((volatile short *)(FPGA2_BASE | 0x132))) //Variable for prescaler divisions -amount of prescaled clocks clk input of prescaler of signal debouncer of the limit switch. 14bits //Watchdog #define F2_Watchdog_reg (*((volatile short *)(FPGA2_BASE | 0x140)))//Watchdog enable bit, watchdog value #define F2_Moto_Driver_SPI_DIRECTION1 (*((volatile short *)(FPGA2_BASE | 0x150))) // //read SSR1 - SSR9 #define F2_CTRL_bus1_reg (*((volatile short *)(FPGA2_BASE | 0x170))) //This Register stores the ssr with n_heater_wd_expire value - read of the value of SSR1 - SSR9 //SSI #define F2_DISPENSER_ROTENC_DATA_p_1_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x180))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_1_RX_msb (*((volatile short *)(FPGA2_BASE | 0x182))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_1_TX (*((volatile short *)(FPGA2_BASE | 0x18E))) //This register triggers a TX transmission #define F2_DISPENSER_ROTENC_DATA_p_2_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x190))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_2_RX_msb (*((volatile short *)(FPGA2_BASE | 0x192))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_2_TX (*((volatile short *)(FPGA2_BASE | 0x19E))) //This register triggers a TX transmission #define F2_DISPENSER_ROTENC_DATA_p_3_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x1A0))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_3_RX_msb (*((volatile short *)(FPGA2_BASE | 0x1A2))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_3_TX (*((volatile short *)(FPGA2_BASE | 0x1AE))) //This register triggers a TX transmission #define F2_DISPENSER_ROTENC_DATA_p_4_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x1B0))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_4_RX_msb (*((volatile short *)(FPGA2_BASE | 0x1B2))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_4_TX (*((volatile short *)(FPGA2_BASE | 0x1BE))) //This register triggers a TX transmission #define F2_DISPENSER_ROTENC_DATA_p_5_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x1C0))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_5_RX_msb (*((volatile short *)(FPGA2_BASE | 0x1C2))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_5_TX (*((volatile short *)(FPGA2_BASE | 0x1CE))) //This register triggers a TX transmission #define F2_DISPENSER_ROTENC_DATA_p_6_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x1D0))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_6_RX_msb (*((volatile short *)(FPGA2_BASE | 0x1D2))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_6_TX (*((volatile short *)(FPGA2_BASE | 0x1DE))) //This register triggers a TX transmission #define F2_DISPENSER_ROTENC_DATA_p_7_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x1E0))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_7_RX_msb (*((volatile short *)(FPGA2_BASE | 0x1E2))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_7_TX (*((volatile short *)(FPGA2_BASE | 0x1EE))) //This register triggers a TX transmission #define F2_DISPENSER_ROTENC_DATA_p_8_RX_lsb (*((volatile short *)(FPGA2_BASE | 0x1F0))) //The 16 Lsb bits of the shifted in data. #define F2_DISPENSER_ROTENC_DATA_p_8_RX_msb (*((volatile short *)(FPGA2_BASE | 0x1F2))) //16 bit MSB if nessesary #define F2_DISPENSER_ROTENC_DATA_p_8_TX (*((volatile short *)(FPGA2_BASE | 0x1FE))) //This register triggers a TX transmission //ANALOG_DYEINGH_TEMP1_1 #define F2_ANALOG_DYEINGH_TEMP1_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x200))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP1_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x202))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP1_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x204))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DYEINGH_TEMP1_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x206))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DYEINGH_TEMP1_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x208))) //The amount of spi words (usually byte sized) per transmission. //AN_ENCLOSURETEMP1_1 #define F2_AN_ENCLOSURETEMP1_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x210))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_AN_ENCLOSURETEMP1_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x212))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_AN_ENCLOSURETEMP1_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x214))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_AN_ENCLOSURETEMP1_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x216))) //The 16 Lsb bits of the shifted in data. #define F2_AN_ENCLOSURETEMP1_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x218))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_DYEINGH_TEMP2 #define F2_ANALOG_DYEINGH_TEMP2_TX_00 (*((volatile short *)(FPGA2_BASE | 0x220))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP2_TX_01 (*((volatile short *)(FPGA2_BASE | 0x222))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP2_RX_00 (*((volatile short *)(FPGA2_BASE | 0x224))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DYEINGH_TEMP2_RX_01 (*((volatile short *)(FPGA2_BASE | 0x226))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DYEINGH_TEMP2_WORDS (*((volatile short *)(FPGA2_BASE | 0x228))) //The amount of spi words (usually byte sized) per transmission. //AN_ENCLOSURETEMP2_1 #define F2_AN_ENCLOSURETEMP2_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x230))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_AN_ENCLOSURETEMP2_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x232))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_AN_ENCLOSURETEMP2_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x234))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_AN_ENCLOSURETEMP2_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x236))) //The 16 Lsb bits of the shifted in data. #define F2_AN_ENCLOSURETEMP2_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x238))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_DYEINGH_TEMP3 #define F2_ANALOG_DYEINGH_TEMP3_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x240))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP3_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x242))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP3_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x244))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DYEINGH_TEMP3_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x246))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DYEINGH_TEMP3_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x248))) //The amount of spi words (usually byte sized) per transmission. //AN_ENCLOSURETEMP3_1 #define F2_AN_ENCLOSURETEMP3_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x250))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_AN_ENCLOSURETEMP3_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x252))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_AN_ENCLOSURETEMP3_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x254))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_AN_ENCLOSURETEMP3_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x256))) //The 16 Lsb bits of the shifted in data. #define F2_AN_ENCLOSURETEMP3_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x258))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_DYEINGH_TEMP4 #define F2_ANALOG_DYEINGH_TEMP4_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x260))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP4_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x262))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP4_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x264))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DYEINGH_TEMP4_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x266))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DYEINGH_TEMP4_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x268))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_DRYER_TEMP1 #define F2_ANALOG_DRYER_TEMP1_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x270))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DRYER_TEMP1_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x272))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DRYER_TEMP1_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x274))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DRYER_TEMP1_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x276))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DRYER_TEMP1_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x278))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_DYEINGH_TEMP5 #define F2_ANALOG_DYEINGH_TEMP5_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x280))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP5_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x282))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DYEINGH_TEMP5_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x284))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DYEINGH_TEMP5_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x286))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DYEINGH_TEMP5_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x288))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_DRYER_TEMP2 #define F2_ANALOG_DRYER_TEMP2_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x290))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DRYER_TEMP2_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x292))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DRYER_TEMP2_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x294))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DRYER_TEMP2_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x296))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DRYER_TEMP2_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x298))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_MIXCHIP_TEMP #define F2_ANALOG_MIXCHIP_TEMP_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x2A0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_MIXCHIP_TEMP_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x2A2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_MIXCHIP_TEMP_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x2A4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_MIXCHIP_TEMP_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x2A6))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_MIXCHIP_TEMP_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x2A8))) //The amount of spi words (usually byte sized) per transmission. //ANALOG_DRYER_TEMP3 #define F2_ANALOG_DRYER_TEMP3_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x2B0))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DRYER_TEMP3_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x2B2))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_ANALOG_DRYER_TEMP3_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x2B4))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_ANALOG_DRYER_TEMP3_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x2B6))) //The 16 Lsb bits of the shifted in data. #define F2_ANALOG_DRYER_TEMP3_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x2B8))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1 #define F2_MOTO_DISPENSER_A1_1_TX_00 (*((volatile short *)(FPGA2_BASE | 0x320))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_1_TX_01 (*((volatile short *)(FPGA2_BASE | 0x322))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_1_RX_00 (*((volatile short *)(FPGA2_BASE | 0x324))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_1_RX_01 (*((volatile short *)(FPGA2_BASE | 0x326))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_1_WORDS (*((volatile short *)(FPGA2_BASE | 0x328))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1_2 #define F2_MOTO_DISPENSER_A1_2_TX_00 (*((volatile short *)(FPGA2_BASE | 0x330))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_2_TX_01 (*((volatile short *)(FPGA2_BASE | 0x332))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_2_RX_00 (*((volatile short *)(FPGA2_BASE | 0x334))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_2_RX_01 (*((volatile short *)(FPGA2_BASE | 0x336))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_2_WORDS (*((volatile short *)(FPGA2_BASE | 0x338))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1_3 #define F2_MOTO_DISPENSER_A1_3_TX_00 (*((volatile short *)(FPGA2_BASE | 0x340))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_3_TX_01 (*((volatile short *)(FPGA2_BASE | 0x342))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_3_RX_00 (*((volatile short *)(FPGA2_BASE | 0x344))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_3_RX_01 (*((volatile short *)(FPGA2_BASE | 0x346))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_3_WORDS (*((volatile short *)(FPGA2_BASE | 0x348))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1_4 #define F2_MOTO_DISPENSER_A1_4_TX_00 (*((volatile short *)(FPGA2_BASE | 0x350))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_4_TX_01 (*((volatile short *)(FPGA2_BASE | 0x352))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_4_RX_00 (*((volatile short *)(FPGA2_BASE | 0x354))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_4_RX_01 (*((volatile short *)(FPGA2_BASE | 0x356))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_4_WORDS (*((volatile short *)(FPGA2_BASE | 0x358))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1_5 #define F2_MOTO_DISPENSER_A1_5_TX_00 (*((volatile short *)(FPGA2_BASE | 0x360))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_5_TX_01 (*((volatile short *)(FPGA2_BASE | 0x362))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_5_RX_00 (*((volatile short *)(FPGA2_BASE | 0x364))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_5_RX_01 (*((volatile short *)(FPGA2_BASE | 0x366))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_5_WORDS (*((volatile short *)(FPGA2_BASE | 0x368))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1_6 #define F2_MOTO_DISPENSER_A1_6_TX_00 (*((volatile short *)(FPGA2_BASE | 0x370))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_6_TX_01 (*((volatile short *)(FPGA2_BASE | 0x372))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_6_RX_00 (*((volatile short *)(FPGA2_BASE | 0x374))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_6_RX_01 (*((volatile short *)(FPGA2_BASE | 0x376))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_6_WORDS (*((volatile short *)(FPGA2_BASE | 0x378))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1_7 #define F2_MOTO_DISPENSER_A1_7_TX_00 (*((volatile short *)(FPGA2_BASE | 0x380))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_7_TX_01 (*((volatile short *)(FPGA2_BASE | 0x382))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_7_RX_00 (*((volatile short *)(FPGA2_BASE | 0x384))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_7_RX_01 (*((volatile short *)(FPGA2_BASE | 0x386))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_7_WORDS (*((volatile short *)(FPGA2_BASE | 0x388))) //The amount of spi words (usually byte sized) per transmission. //MOTO_DISPENSER_A1_8 #define F2_MOTO_DISPENSER_A1_8_TX_00 (*((volatile short *)(FPGA2_BASE | 0x390))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_8_TX_01 (*((volatile short *)(FPGA2_BASE | 0x392))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F2_MOTO_DISPENSER_A1_8_RX_00 (*((volatile short *)(FPGA2_BASE | 0x394))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F2_MOTO_DISPENSER_A1_8_RX_01 (*((volatile short *)(FPGA2_BASE | 0x396))) //The 16 Lsb bits of the shifted in data. #define F2_MOTO_DISPENSER_A1_8_WORDS (*((volatile short *)(FPGA2_BASE | 0x398))) //The amount of spi words (usually byte sized) per transmission. #define F2_Tacho_reg0 (*((volatile short *)(FPGA2_BASE | 0x3C0))) //This Register stores the Tacho counter //Prescaler #define F2_Prescaler1_reg0 (*((volatile short *)(FPGA2_BASE | 0x3E0))) //Parameter for prescaler divisions - 6bit ssi high duty cycle value for prescaler #define F2_Prescaler1_reg1 (*((volatile short *)(FPGA2_BASE | 0x3E2))) //Parameter for prescaler divisions - 6bit ssi low duty cycle value for prescaler #define F2_Prescaler1_reg2 (*((volatile short *)(FPGA2_BASE | 0x3E4))) //Parameter for prescaler divisions - 3bit spi temp low duty cycle value for pmw #define F2_Prescaler1_reg3 (*((volatile short *)(FPGA2_BASE | 0x3E6))) //Parameter for prescaler divisions - 3bit spi temp high duty cycle value for pmw #define F2_Prescaler1_reg4 (*((volatile short *)(FPGA2_BASE | 0x3E8))) //Parameter for prescaler divisions - 3bit spi moto low duty cycle value for pmw #define F2_Prescaler1_reg5 (*((volatile short *)(FPGA2_BASE | 0x3EA))) //Parameter for prescaler divisions - 3bit spi moto high duty cycle value for pmw #define F2_Prescaler1_reg6 (*((volatile short *)(FPGA2_BASE | 0x3EC))) //Parameter for prescaler divisions - 8bit BLOWER low duty cycle value for pmw #define F2_Prescaler1_reg7 (*((volatile short *)(FPGA2_BASE | 0x3EE))) //Parameter for prescaler divisions - 8bit BLOWER high duty cycle value for pmw //Test #define F2_Test (*((volatile short *)(FPGA2_BASE | 0x3F0))) //Readback not - gives the inverse of the written to value // * * * * * * * * * * * * * * * * FPGA 3 * * * * * * * * * * * * * * * * // //Version1 #define F3_Ver1_D (*((volatile short *)(FPGA3_BASE | 0x000))) //Version of Fpga is held here //Version2 #define F3_Ver2_D (*((volatile short *)(FPGA3_BASE | 0x010))) //Version of Fpga is held here //GPI 01 #define F3_GPI_01_D (*((volatile short *)(FPGA3_BASE | 0x020))) //Reads the direct values that are currently being sent to the fpga. #define F3_GPI_01_L (*((volatile short *)(FPGA3_BASE | 0x022))) //Value of the latched shorterrupts that have occurred #define F3_GPI_01_M (*((volatile short *)(FPGA3_BASE | 0x024))) //Value of the shorterrupt mask, Default is 0x0000 //MIDTANK 01 #define F3_MIDTANK_01_Direct (*((volatile short *)(FPGA3_BASE | 0x030))) //Reads the direct values that are currently being sent to the fpga. #define F3_MIDTANK_01_Latched (*((volatile short *)(FPGA3_BASE | 0x032))) //Value of the latched shorterrupts that have occurred #define F3_MIDTANK_01_Mask (*((volatile short *)(FPGA3_BASE | 0x034))) //Value of the shorterrupt mask, Default is 0x0000 //MIDTANK 02 #define F3_MIDTANK_02_Direct (*((volatile short *)(FPGA3_BASE | 0x040))) //Reads the direct values that are currently being sent to the fpga. #define F3_MIDTANK_02_Latched (*((volatile short *)(FPGA3_BASE | 0x042))) //Value of the latched shorterrupts that have occurred #define F3_MIDTANK_02_Mask (*((volatile short *)(FPGA3_BASE | 0x044))) //Value of the shorterrupt mask, Default is 0x0000 //DISPENSER_ROTENC_IN #define F3_DISPENSER_ROTENC_IN_Direct (*((volatile short *)(FPGA3_BASE | 0x050))) //Reads the direct values that are currently being sent to the fpga. #define F3_DISPENSER_ROTENC_IN_Latched (*((volatile short *)(FPGA3_BASE | 0x052))) //Value of the latched shorterrupts that have occurred #define F3_DISPENSER_ROTENC_IN_Mask (*((volatile short *)(FPGA3_BASE | 0x054))) //Value of the shorterrupt mask, Default is 0x0000 //Moto_Driver_NBUSY_register1 #define F3_Moto_Driver_NBUSY1_D (*((volatile short *)(FPGA3_BASE | 0x060))) //Reads the direct values that are currently being sent to the fpga. #define F3_Moto_Driver_NBUSY1_L (*((volatile short *)(FPGA3_BASE | 0x062))) //Value of the latched shorterrupts that have occurred #define F3_Moto_Driver_NBUSY1_M (*((volatile short *)(FPGA3_BASE | 0x064))) //Value of the shorterrupt mask, Default is 0x0000 //CARTx_PRES #define F3_CARTx_PRES_02_Direct (*((volatile short *)(FPGA3_BASE | 0x070))) //Reads the direct values that are currently being sent to the fpga. #define F3_CARTx_PRES_02_Latched (*((volatile short *)(FPGA3_BASE | 0x072))) //Value of the latched shorterrupts that have occurred #define F3_CARTx_PRES_02_Mask (*((volatile short *)(FPGA3_BASE | 0x074))) //Value of the shorterrupt mask, Default is 0x0000 //LS_01 #define F3_LS_01_Direct (*((volatile short *)(FPGA3_BASE | 0x080))) //Reads the direct values that are currently being sent to the fpga. #define F3_LS_01_Latched (*((volatile short *)(FPGA3_BASE | 0x082))) //Value of the latched shorterrupts that have occurred #define F3_LS_01_Mask (*((volatile short *)(FPGA3_BASE | 0x084))) //Value of the shorterrupt mask, Default is 0x0000 //GPI_02 #define F3_GPI_02_Direct (*((volatile short *)(FPGA3_BASE | 0x090))) //Reads the direct values that are currently being sent to the fpga. #define F3_GPI_02_Latched (*((volatile short *)(FPGA3_BASE | 0x092))) //Value of the latched shorterrupts that have occurred #define F3_GPI_02_Mask (*((volatile short *)(FPGA3_BASE | 0x094))) //Value of the shorterrupt mask, Default is 0x0000 //Spi_Busy_01 #define F3_SPI_Busy1_D (*((volatile short *)(FPGA3_BASE | 0x0A0))) //Reads the direct values that are currently being sent to the fpga. #define F3_SPI_Busy1_L (*((volatile short *)(FPGA3_BASE | 0x0A2))) //Value of the latched shorterrupts that have occurred #define F3_SPI_Busy1_M (*((volatile short *)(FPGA3_BASE | 0x0A4))) //Value of the shorterrupt mask, Default is 0x0000 //Moto_Driver_NSTBYRST_register1 #define F3_Moto_Driver_NSTBYRST1 (*((volatile short *)(FPGA3_BASE | 0x0B2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //GPO_01 #define F3_GPO_01_bus (*((volatile short *)(FPGA3_BASE | 0x0C2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //Moto_Driver_SW_register1 #define F3_Moto_Driver_SW1 (*((volatile short *)(FPGA3_BASE | 0x0D2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //VALVE_OUT #define F3_VALVE_OUT (*((volatile short *)(FPGA3_BASE | 0x0E2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //DISPENSER_ROTENC_OUT #define F3_DISPENSER_ROTENC_OUT (*((volatile short *)(FPGA3_BASE | 0x0F2))) //Writes to values. Readback thevaluessthat are currently in the GPO register //QEI_SCREW_ROTENC #define F3_SPARE1_ROTENC_lsb (*((volatile short *)(FPGA3_BASE | 0x100))) //Value of the lsb of the QEI register #define F3_SPARE1_ROTENC_msb (*((volatile short *)(FPGA3_BASE | 0x102))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F3_SPARE1_ROTENC_index (*((volatile short *)(FPGA3_BASE | 0x104))) //value of index counter //QEI_RSPARE_ROTENC #define F3_RSPARE_ROTENC_lsb (*((volatile short *)(FPGA3_BASE | 0x110))) //Value of the lsb of the QEI register #define F3_RSPARE_ROTENC_msb (*((volatile short *)(FPGA3_BASE | 0x112))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved #define F3_RSPARE_ROTENC_index (*((volatile short *)(FPGA3_BASE | 0x114))) //value of index counter //WATCHDOG #define F3_Watchdog_reg (*((volatile short *)(FPGA3_BASE | 0x140)))//Watchdog enable bit, watchdog value - F3_GPO_01_bus BIT4 DYEINGH_SSR11_CTRL HeadHeaterZ6 //GPO #define F3_GPO_02_bus (*((volatile short *)(FPGA3_BASE | 0x150)))//General purpose GPIO register //SPI_MOTO_RLOADING_A1 #define F3_MOTO_SPARE1_1_A1_TX_00 (*((volatile short *)(FPGA3_BASE | 0x200))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE1_1_A1_TX_01 (*((volatile short *)(FPGA3_BASE | 0x202))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE1_1_A1_RX_00 (*((volatile short *)(FPGA3_BASE | 0x204))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F3_MOTO_SPARE1_1_A1_RX_01 (*((volatile short *)(FPGA3_BASE | 0x206))) //The 16 Lsb bits of the shifted in data. #define F3_MOTO_SPARE1_1_A1_WORDS (*((volatile short *)(FPGA3_BASE | 0x208))) //The amount of spi words (usually byte sized) per transmission. //SPI_MOTO_RDRIVING_A1 #define F3_MOTO_SPARE1_2_A1_TX_00 (*((volatile short *)(FPGA3_BASE | 0x210))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE1_2_A1_TX_01 (*((volatile short *)(FPGA3_BASE | 0x212))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE1_2_A1_RX_00 (*((volatile short *)(FPGA3_BASE | 0x214))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F3_MOTO_SPARE1_2_A1_RX_01 (*((volatile short *)(FPGA3_BASE | 0x216))) //The 16 Lsb bits of the shifted in data. #define F3_MOTO_SPARE1_2_A1_WORDS (*((volatile short *)(FPGA3_BASE | 0x218))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_LDRIVING_A1 #define F3_MOTO_SPARE2_1_A1_TX_00 (*((volatile short *)(FPGA3_BASE | 0x220))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE2_1_A1_TX_01 (*((volatile short *)(FPGA3_BASE | 0x222))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE2_1_A1_RX_00 (*((volatile short *)(FPGA3_BASE | 0x224))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F3_MOTO_SPARE2_1_A1_RX_01 (*((volatile short *)(FPGA3_BASE | 0x226))) //The 16 Lsb bits of the shifted in data. #define F3_MOTO_SPARE2_1_A1_WORDS (*((volatile short *)(FPGA3_BASE | 0x228))) //The amount of spi words (usually byte sized) per transmission. //SPI_F1_MOTO_LLOADING_A1 #define F3_MOTO_SPARE2_2_A1_TX_00 (*((volatile short *)(FPGA3_BASE | 0x230))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE2_2_A1_TX_01 (*((volatile short *)(FPGA3_BASE | 0x232))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE2_2_A1_RX_00 (*((volatile short *)(FPGA3_BASE | 0x234))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F3_MOTO_SPARE2_2_A1_RX_01 (*((volatile short *)(FPGA3_BASE | 0x236))) //The 16 Lsb bits of the shifted in data. #define F3_MOTO_SPARE2_2_A1_WORDS (*((volatile short *)(FPGA3_BASE | 0x238))) //The amount of spi words (usually byte sized) per transmission. #define F3_MOTO_SPARE3_1_A1_TX_00 (*((volatile short *)(FPGA3_BASE | 0x240))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE3_1_A1_TX_01 (*((volatile short *)(FPGA3_BASE | 0x242))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first. #define F3_MOTO_SPARE3_1_A1_RX_00 (*((volatile short *)(FPGA3_BASE | 0x244))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros. #define F3_MOTO_SPARE3_1_A1_RX_01 (*((volatile short *)(FPGA3_BASE | 0x246))) //The 16 Lsb bits of the shifted in data. #define F3_MOTO_SPARE3_1_A1_WORDS (*((volatile short *)(FPGA3_BASE | 0x248))) //The amount of spi words (usually byte sized) per transmission. //SSI #define F3_SPARE1_ROTENC_DATA_p_1_RX_lsb (*((volatile short *)(FPGA3_BASE | 0x2C0))) //The 16 Lsb bits of the shifted in data. #define F3_SPARE1_ROTENC_DATA_p_1_RX_msb (*((volatile short *)(FPGA3_BASE | 0x2C2))) //16 bit MSB if nessesary #define F3_SPARE1_ROTENC_DATA_p_1_TX (*((volatile short *)(FPGA3_BASE | 0x2CE))) //This register triggers a TX transmission #define F3_SPARE2_ROTENC_DATA_p_2_RX_lsb (*((volatile short *)(FPGA3_BASE | 0x2D0))) //The 16 Lsb bits of the shifted in data. #define F3_SPARE2_ROTENC_DATA_p_2_RX_msb (*((volatile short *)(FPGA3_BASE | 0x2D2))) //16 bit MSB if nessesary #define F3_SPARE2_ROTENC_DATA_p_2_TX (*((volatile short *)(FPGA3_BASE | 0x2DE))) //This register triggers a TX transmission //Control the motors clock source due to EMC issues #define F3_MOTO_CLK_SRC_SEL (*((volatile short *)(FPGA3_BASE | 0x370))) //bit that control motors source selects 32Mhz or low #define F3_Moto_Driver_SPI_DIRECTION1 (*((volatile short *)(FPGA3_BASE | 0x380))) //This bit control of the direction of SDIO 0-4 //PWM LEDS FPGA VER 050219 #define F3_low_var_LED1 (*((volatile short *)(FPGA3_BASE | 0x390))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw #define F3_high_var_LED1 (*((volatile short *)(FPGA3_BASE | 0x392))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw #define F3_low_var_LED2 (*((volatile short *)(FPGA3_BASE | 0x394))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw #define F3_high_var_LED2 (*((volatile short *)(FPGA3_BASE | 0x396))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw #define F3_low_var_LED3 (*((volatile short *)(FPGA3_BASE | 0x398))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw #define F3_high_var_LED3 (*((volatile short *)(FPGA3_BASE | 0x39A))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw #define F3_low_var_LED4 (*((volatile short *)(FPGA3_BASE | 0x39C))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw #define F3_high_var_LED4 (*((volatile short *)(FPGA3_BASE | 0x39E))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw #define F3_low_var_SPARE1_1 (*((volatile short *)(FPGA3_BASE | 0x3A0))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw - unused according the costumer request #define F3_high_var_SPARE1_1 (*((volatile short *)(FPGA3_BASE | 0x3A2))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw - unused according the costumer reques #define F3_low_var_SPARE1_2 (*((volatile short *)(FPGA3_BASE | 0x3A4))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw #define F3_high_var_SPARE1_2 (*((volatile short *)(FPGA3_BASE | 0x3A6))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw #define F3_low_var_SPARE2_1 (*((volatile short *)(FPGA3_BASE | 0x3A8))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw #define F3_high_var_SPARE2_1 (*((volatile short *)(FPGA3_BASE | 0x3AA))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw #define F3_low_var_SPARE2_2 (*((volatile short *)(FPGA3_BASE | 0x3AC))) //Parameter for prescaler divisions - 8bit low duty cycle value for pmw #define F3_high_var_SPARE2_2 (*((volatile short *)(FPGA3_BASE | 0x3AE))) //Parameter for prescaler divisions - 8bit high duty cycle value for pmw //read SSR11 #define F3_CTRL_bus1_reg (*((volatile short *)(FPGA3_BASE | 0x3B0))) //This Register stores the ssr with n_heater_wd_expire value - read of the value of F3_GPO_EXTWINDER_SSR11_CTRL // #define F3_Prescaler1_reg9 (*((volatile short *)(FPGA3_BASE | 0x3C2))) //Variable for prescaler divisions -amount of prescaled clocks clk input of prescaler of signal debouncer of the limit switch. 14bits. The value inserted here is multiply by 8 before being set. #define F3_SW_RESET_reg (*((volatile short *)(FPGA3_BASE | 0x3D0))) //This register resets the MCU //Prescaler #define F3_Prescaler1_reg1 (*((volatile short *)(FPGA3_BASE | 0x3E0))) //Parameter for prescaler divisions - 6bit ssi high duty cycle value for prescale #define F3_Prescaler1_reg2 (*((volatile short *)(FPGA3_BASE | 0x3E2))) //Parameter for prescaler divisions - 6bit ssi low duty cycle value for prescaler #define F3_Prescaler1_reg3 (*((volatile short *)(FPGA3_BASE | 0x3E4))) //Parameter for prescaler divisions - 3bit spi moto low duty cycle value for pmw #define F3_Prescaler1_reg4 (*((volatile short *)(FPGA3_BASE | 0x3E6))) //Parameter for prescaler divisions - 3bit spi moto high duty cycle value for pmw #define F3_Prescaler1_reg5 (*((volatile short *)(FPGA3_BASE | 0x3E8))) //Parameter for prescaler divisions #define F3_Prescaler1_reg6 (*((volatile short *)(FPGA3_BASE | 0x3EA))) //Parameter for prescaler divisions #define F3_Prescaler1_reg7 (*((volatile short *)(FPGA3_BASE | 0x3EC))) //Parameter for prescaler divisions #define F3_Prescaler1_reg8 (*((volatile short *)(FPGA3_BASE | 0x3EE))) //Parameter for prescaler divisions //Test #define F3_Test (*((volatile short *)(FPGA3_BASE | 0x3F0))) //Readback not - gives the inverse of the written to value // ----------------------- BLOWER ----------------------- #define GPI_BLOWER_TACH F2_Tacho_reg0 //WHS GPO_BLOWER_PWM - See the stub "GPO_BLOWER_PWM.cs" #define GPO_BLOWER_PWM_FREQ F2_Prescaler1_reg11 #define GPO_BLOWER_PWM_LOW F2_Prescaler1_reg6 #define GPO_BLOWER_PWM_HIGH F2_Prescaler1_reg7 // ----------------------- LEDS ----------------------- #define F3_LOw_Cart_Led1 F3_low_var_SPARE1_2 #define F3_High_Cart_Led1 F3_high_var_SPARE1_2 #define F3_LOw_Cart_Led2 F3_low_var_SPARE2_1 #define F3_High_Cart_Led2 F3_high_var_SPARE2_1 #define F3_LOw_Cart_Led3 F3_low_var_SPARE2_2 #define F3_High_Cart_Led3 F3_high_var_SPARE2_2 //F3_LS_01_Direct typedef union { struct { bool F3_LS_SPARE2_4 : 1; //0 bool F3_LS_SPARE2_3 : 1; //1 bool F3_LS_SPARE2_2 : 1; //2 bool F3_LS_SPARE2_1 : 1; //3 bool F3_LS_SPARE1_4 : 1; //4 bool F3_LS_SPARE1_3 : 1; //5 bool F3_LS_SPARE1_2 : 1; //6 bool F3_LS_SPARE1_1 : 1; //7 char F3_LS_01_RESERVE : 8; //8-16 }bits; unsigned short ushort; }F3_LS_01; //F3_GPI_02_Direct typedef union { struct { bool F3_GPI_TACTSW4 : 1; //0 bool F3_GPI_TACTSW3 : 1; //1 bool Thread_Jogging_Switch : 1; //2 (F3_GPI_TACTSW2) bool Thread_Load_Switch : 1; //3 (F3_GPI_TACTSW1) unsigned short F3_GPI_02_RESERVE : 12; //4-16 }bits; unsigned short ushort; }F3_GPI_02; //1 Version1_Direct typedef union { struct { unsigned char Month; //0-7 unsigned char Day; //8-15 }bytes; unsigned short ushort; }VER1; //4 Version2_Direct typedef union { struct { unsigned char Ver_num; //0-7 unsigned char Year; //8-15 }bytes; unsigned short ushort; }VER2; //F1_Moto_Driver_NBUSY1_Direct typedef union { struct { bool F1_MOTO_LPIVOT1_A1_NBUSY : 1; //0 bool F1_MOTO_LLOADING_A1_NBUSY : 1; //1 bool F1_MOTO_LDRIVING_A1_NBUSY : 1; //2 bool F1_MOTO_LDANCER2_A1_NBUSY : 1; //3 bool F1_MOTO_LDANCER1_A1_NBUSY : 1; //4 bool F1_MOTO_DRYER_LOADARM_A1_NBUSY : 1; //5 bool F1_MOTO_DRYER_LID_A1_NBUSY : 1; //6 bool F1_MOTO_DRYER_DRIVING_A1_NBUSY : 1; //7 bool F1_MOTO_DH_LID_A1_NBUSY : 1; //8 bool F1_MOTO_DH_CLEANMECH_A1_NBUSY : 1; //9 bool F1_MOTO_DH_CLEANHEAD_A1_NBUSY : 1; //10 unsigned char RESERVE:5; //11-15 }bits; unsigned short ushort; }F1MOTNBUSY1; //19 F1_Moto_Driver_NBUSY2_Direct typedef union { struct { bool F1_MOTO_WINDER_A1_NBUSY : 1; //0 bool F1_MOTO_SCREW_A1_NBUSY : 1; //1 bool F1_MOTO_RLOADING_A1_NBUSY : 1; //2 bool F1_MOTO_RLOADARM_A1_NBUSY : 1; //3 bool F1_MOTO_RDRIVING_A1_NBUSY : 1; //4 bool F1_MOTO_RDANCER_A1_NBUSY : 1; //5 unsigned char RESERVE1 : 2; // 6-7 unsigned char RESERVE2; // 8-15 }bits; unsigned short ushort; }F1MOTNBUSY2; //F2_Moto_Driver_NBUSY1_Direct typedef union { struct { bool F2_MOTO_DISPENSER_A1_8_NBUSY : 1; //0 bool F2_MOTO_DISPENSER_A1_7_NBUSY : 1; //1 bool F2_MOTO_DISPENSER_A1_6_NBUSY : 1; //2 bool F2_MOTO_DISPENSER_A1_5_NBUSY : 1; //3 bool F2_MOTO_DISPENSER_A1_4_NBUSY : 1; //4 bool F2_MOTO_DISPENSER_A1_3_NBUSY : 1; //5 bool F2_MOTO_DISPENSER_A1_2_NBUSY : 1; //6 bool F2_MOTO_DISPENSER_A1_1_NBUSY : 1; //7 unsigned char RESERVE:5; //8-15 }bits; unsigned short ushort; }F2MOTNBUSY1; //F3_Moto_Driver_NBUSY1_Direct typedef union { struct { bool F3_MOTO_SPARE1_1_A1_NBUSY : 1; //0 bool F3_MOTO_SPARE1_2_A1_NBUSY : 1; //1 bool F3_MOTO_SPARE2_1_A1_NBUSY : 1; //2 bool F3_MOTO_SPARE2_2_A1_NBUSY : 1; //3 bool F3_MOTO_SPARE3_1_A1_NBUSY : 1; //4 unsigned char RESERVE1 : 3; //5-7 unsigned char RESERVE : 5; //8-15 }bits; unsigned short ushort; }F3MOTNBUSY1; //------------------------------------------------------------- //F1_SPI_Busy1_Direct typedef union { struct { bool F1_RSPARE_ROTENC_DATA_p_busy : 1; //0 bool F1_LSPARE_ROTENC_DATA_p_busy : 1; //1 bool F1_RDANCER_ROTENC_DATA_p_busy : 1; //2 bool F1_LDANCER2_ROTENC_DATA_p_busy : 1; //3 bool F1_LDANCER1_ROTENC_DATA_p_busy : 1; //4 bool F1_MOTO_RLOADING_A1_SDI_busy : 1; //5 bool F1_MOTO_RDRIVING_A1_SDI_busy : 1; //6 bool F1_MOTO_DRYER_DRIVING_A1_SDI_busy : 1; //7 bool F1_MOTO_WINDER_A1_SDI_busy : 1; //8 bool F1_MOTO_LDANCER2_A1_SDI_busy : 1; //9 bool F1_MOTO_LDRIVING_A1_SDI_busy : 1; //10 bool F1_MOTO_DH_CLEANHEAD_A1_SDI_busy : 1; //11 bool F1_MOTO_RLOADARM_A1_SDI_busy : 1; //12 bool F1_MOTO_DRYER_LID_A1_SDI_busy : 1; //13 bool F1_MOTO_LLOADING_A1_SDI_busy : 1; //14 bool F1_MOTO_DH_CLEANMECH_A1_SDI_busy : 1; //15 }bits; unsigned short ushort; }F1SPIBUSY1; //F2_SPI_Busy1_Direct typedef union { struct { bool F2_ANALOG_DRYER_TEMP1_1_BUSY : 1; //0 bool F2_ANALOG_DRYER_TEMP2_1_BUSY : 1; //1 bool F2_ANALOG_DRYER_TEMP3_1_BUSY : 1; //2 bool F2_ANALOG_DYEINGH_TEMP1_1_BUSY : 1; //3 bool F2_ANALOG_DYEINGH_TEMP2_1_BUSY : 1; //4 bool F2_ANALOG_DYEINGH_TEMP3_1_BUSY : 1; //5 bool F2_ANALOG_DYEINGH_TEMP4_1_BUSY : 1; //6 bool F2_ANALOG_DYEINGH_TEMP5_1_BUSY : 1; //7 bool F2_ANALOG_MIXCHIP_TEMP_1_BUSY : 1; //8 bool F2_AN_ENCLOSURETEMP1_1_BUSY : 1; //9 bool F2_AN_ENCLOSURETEMP2_1_BUSY : 1; //10 bool F2_AN_ENCLOSURETEMP3_1_BUSY : 1; //11 bool spi_busy12 : 1; //12 bool spi_busy13 : 1; //13 bool spi_busy14 : 1; //14 bool spi_busy15 : 1; //15 }bits; unsigned short ushort; }F2SPIBUSY1; //F1_SPI_Busy2_Direct typedef union { struct { bool F1_MOTO_RDANCER_A1_SDI_busy : 1; //0 bool F1_MOTO_DH_LID_A1_SDI_busy : 1; //1 bool F1_MOTO_DRYER_LOADARM_A1_SDI_busy : 1; //2 bool F1_MOTO_SCREW_A1_SDI_busy : 1; //3 bool F1_MOTO_LDANCER1_A1_SDI_busy : 1; //4 bool F1_MOTO_LPIVOT1_A1_SDI_busy : 1; //5 bool spi_busy22 : 1; //6 bool spi_busy23 : 1; //7 bool spi_busy24 : 1; //8 bool spi_busy25 : 1; //9 bool spi_busy26 : 1; //10 bool spi_busy27 : 1; //11 bool spi_busy28 : 1; //12 bool spi_busy29 : 1; //13 bool spi_busy30 : 1; //14 bool spi_busy31 : 1; //15 }bits; unsigned short ushort; }F1SPIBUSY2; //F2_SPI_Busy2_Direct typedef union { struct { bool spi_busy16 : 1; //0 bool spi_busy17 : 1; //1 bool spi_busy18 : 1; //2 bool spi_busy19 : 1; //3 bool F2_MOTO_DISPENSER_A1_1_BUSY : 1; //4 bool F2_MOTO_DISPENSER_A1_2_BUSY : 1; //5 bool F2_MOTO_DISPENSER_A1_3_BUSY : 1; //6 bool F2_MOTO_DISPENSER_A1_4_BUSY : 1; //7 bool F2_MOTO_DISPENSER_A1_5_BUSY : 1; //8 bool F2_MOTO_DISPENSER_A1_6_BUSY : 1; //9 bool F2_MOTO_DISPENSER_A1_7_BUSY : 1; //10 bool F2_MOTO_DISPENSER_A1_8_BUSY : 1; //11 bool spi_busy28 : 1; //12 bool spi_busy29 : 1; //13 bool spi_busy30 : 1; //14 bool spi_busy31 : 1; //15 }bits; unsigned short ushort; }F2SPIBUSY2; //F3_busy_01_Direct typedef union { struct { bool F3_SPARE2_ROTENC_DATA_p_busy : 1; //0 bool F3_SPARE1_ROTENC_DATA_p_busy : 1; //1 bool F3_MOTO_SPARE1_1_A1_SDI_busy : 1; //2 bool F3_MOTO_SPARE1_2_A1_SDI_busy : 1; //3 bool F3_MOTO_SPARE2_1_A1_SDI_busy : 1; //4 bool F3_MOTO_SPARE2_2_A1_SDI_busy : 1; //5 bool F3_MOTO_SPARE3_1_A1_SDI_busy : 1; //6 bool spi_busy7 : 1; //7 bool spi_busy8 : 1; //8 bool spi_busy9 : 1; //9 bool spi_busy10 : 1; //10 bool spi_busy11 : 1; //11 bool spi_busy12 : 1; //12 bool spi_busy13 : 1; //13 bool spi_busy14 : 1; //14 bool spi_busy15 : 1; //15 }bits; unsigned short ushort; }F3SPIBUSY1; //----------------------------------------------------------- //29 + 32 SPI_Busy_register1 + SPI_Busy_register2 typedef union { struct { unsigned char SPI_Busy_1_D; unsigned char SPI_Busy_2_D; }ushort; unsigned int uint; }SPI_BUSY; //35 Moto_Driver_NSTBYRST1 typedef union { struct { bool LPIVOT1 : 1; //0 bool LLOADING : 1; //1 bool LDRIVING : 1; //2 bool LDANCER2 : 1; //3 bool LDANCER1 : 1; //4 bool DRYER_LOADARM : 1; //5 bool DRYER_LID : 1; //6 bool DRYER_DRIVING : 1; //7 bool DH_LID : 1; //8 bool DH_CLEANMECH : 1; //9 bool DH_CLEANHEAD : 1; //10 unsigned char RESERVE:5; //11-15 }bits; unsigned short ushort; }MOT_NSTBYRST1; //36 Moto_Driver_NSTBYRST2 typedef union { struct { bool WINDER : 1; //0 bool SCREW : 1; //1 bool RLOADING : 1; //2 bool RLOADARM : 1; //3 bool RDRIVING : 1; //4 bool RDANCER : 1; //5 unsigned char RESERVE1:2; // 6-7 unsigned char RESERVE2; // 8-15 }bits; unsigned short ushort; }MOT_NSTBYRST2; //37 Moto_Driver_SW_register1 - F1_Moto_Driver_SW1 typedef union { struct { bool LPIVOT1 : 1; //0 bool LLOADING : 1; //1 bool LDRIVING : 1; //2 bool LDANCER2 : 1; //3 bool LDANCER1 : 1; //4 bool DRYER_LOADARM : 1; //5 bool DRYER_LID : 1; //6 bool DRYER_DRIVING:1; //7 bool DH_LID : 1; //8 bool DH_CLEANMECH : 1; //9 bool DH_CLEANHEAD : 1; //10 bool GPO_DH_MAGNET : 1; //11 //GPO_TFEED_BREAK_1 bool GPO_TFEED_BREAK_2 : 1; //12 unsigned char RESERVE:3; // 13-15 }bits; unsigned short ushort; }MOT_SW1; //38 Moto_Driver_SW_register2 - Moto_Driver_SW2 typedef union { struct { bool F1_MOTO_WINDER_A1_SW : 1; //0 bool F1_MOTO_SCREW_A1_SW : 1; //1 bool F1_MOTO_RLOADING_A1_SW : 1; //2 bool F1_MOTO_RLOADARM_A1_SW : 1; //3 bool F1_MOTO_RDRIVING_A1_SW : 1; //4 bool F1_MOTO_RDANCER_A1_SW : 1; //5 unsigned char RESERVE1:2; // 6-7 unsigned char RESERVE2; // 8-15 }bits; unsigned short ushort; }MOT_SW2; //F3_GPO_01_bus typedef union { struct { bool F3_LUBRICANT_VALVE : 1; //0 //F3_GPO_LED4 bool F3_GPO_LED3 : 1; //1 bool F3_GPO_LED2 : 1; //2 bool F3_GPO_LED1 : 1; //3 bool F3_GPO_EXTWINDER_SSR11_CTRL : 1; //4 bool F3_GPO_BUZZER : 1; //5 bool F3_SPARE2_ROTENC_CLK : 1; //6 bool F3_SPARE1_ROTENC_CLK : 1; //7 unsigned char RESERVE; // 8-15 }bits; unsigned short ushort; }F3_GPO_01_REG; F3_GPO_01_REG F3_GPO_01_Reg; //F3_VALVE_OUT typedef union { //--------------------------// struct // A - Air // { // C - Cartridge // //Dry air Valves // L - Left // bool VALVE_2W_MID_AIR_8 : 1; //0 MIDTANK2MANIF4_VALVE_2 // R - Right // bool VALVE_2W_MID_AIR_4 : 1; //1 MIDTANK2MANIF4_VALVE_1 // F - Front // bool VALVE_2W_MID_AIR_7 : 1; //2 MIDTANK2MANIF3_VALVE_2 // B - Back // bool VALVE_2W_MID_AIR_3 : 1; //3 MIDTANK2MANIF3_VALVE_1 // M - Middle // bool VALVE_2W_MID_AIR_6 : 1; //4 MIDTANK2MANIF2_VALVE_2 // -------------------- // bool VALVE_2W_MID_AIR_2 : 1; //5 MIDTANK2MANIF2_VALVE_1 // A [7] A [8] // bool VALVE_2W_MID_AIR_5 : 1; //6 MIDTANK2MANIF1_VALVE_2 // C [7] C [8] // bool VALVE_2W_MID_AIR_1 : 1; //7 MIDTANK2MANIF1_VALVE_1 // // // A [5] A [6] // bool VALVE_2W_CART_MID_8 : 1; //8 CART2MIDTANK4_VALVE_2 // C [5] C [6] // bool VALVE_2W_CART_MID_4 : 1; //9 CART2MIDTANK4_VALVE_1 // // bool VALVE_2W_CART_MID_7 : 1; //10 CART2MIDTANK3_VALVE_2 // A [3] A [4] // bool VALVE_2W_CART_MID_3 : 1; //11 CART2MIDTANK3_VALVE_1 // C [3] C [4] // bool VALVE_2W_CART_MID_6 : 1; //12 CART2MIDTANK2_VALVE_2 // // bool VALVE_2W_CART_MID_2 : 1; //13 CART2MIDTANK2_VALVE_1 // A [1] A [2] // bool VALVE_2W_CART_MID_5 : 1; //14 CART2MIDTANK1_VALVE_2 // C [1] C [2] // bool VALVE_2W_CART_MID_1 : 1; //15 CART2MIDTANK1_VALVE_1 // // }bits; // FRONT // unsigned short ushort; //--------------------------// }VALVE_GPO_REG; //F1_gpo_01 typedef union { struct { bool F1_GPO_WASTECH_PUMP2 : 1; //0 bool F1_GPO_WHS_WTANKPUMP2 : 1; //1 bool F1_GPO_DYEINGH_SSR10_CTRL : 1; //2 F1_GPO_DILUTORPUMP_SSR10_CTRL bool DRYER_FAN_TORQUE_PWM : 1; //3 F1_GPO_EXTWINDER_3 bool DRYER_FAN_DIRECT : 1; //4 F1_GPO_EXTWINDER_2 bool DRYER_FAN_ON : 1; //5 F1_GPO_EXTWINDER_1 bool F1_VALVE_WASTE_TANK : 1; //6 bool F1_VALVE_MIXCHIP_WASTECH : 1; //7 unsigned char RESERVE; // 8-15 }bits; unsigned short ushort; }F1_GPO_REG; F1_GPO_REG F1_GPO_Reg; //F2_DISPENSER_VALVE_OUT typedef union { struct { bool F2_DISPENSER_VALVE_C1_1_C2_1 : 1;//0 bool F2_DISPENSER_VALVE_C1_2_C2_2 : 1;//1 bool F2_DISPENSER_VALVE_C1_3_C2_3 : 1;//2 bool F2_DISPENSER_VALVE_C1_4_C2_4 : 1;//3 bool F2_DISPENSER_VALVE_C1_5_C2_5 : 1;//4 bool F2_DISPENSER_VALVE_C1_6_C2_6 : 1;//5 bool F2_DISPENSER_VALVE_C1_7_C2_7 : 1;//6 bool F2_DISPENSER_VALVE_C1_8_C2_8 : 1;//7 bool F2_DISPENSER_VALVE_EN_1 : 1;//8 bool F2_DISPENSER_VALVE_EN_2 : 1;//9 bool F2_DISPENSER_VALVE_EN_3 : 1;//10 bool F2_DISPENSER_VALVE_EN_4 : 1;//11 bool F2_DISPENSER_VALVE_EN_5 : 1;//12 bool F2_DISPENSER_VALVE_EN_6 : 1;//13 bool F2_DISPENSER_VALVE_EN_7 : 1;//14 bool F2_DISPENSER_VALVE_EN_8 : 1;//15 }bits; unsigned short ushort; }DISPENSER_VALVE_GPO_REG; //F2_DISPENSER_VALVE_IN_Direct typedef union { struct { //Dispenser Valves OCD bool F2_DISPENSER_VALVE_OCD_8 : 1; //0 bool F2_DISPENSER_VALVE_OCD_7 : 1; //1 bool F2_DISPENSER_VALVE_OCD_6 : 1; //2 bool F2_DISPENSER_VALVE_OCD_5 : 1; //3 bool F2_DISPENSER_VALVE_OCD_4 : 1; //4 bool F2_DISPENSER_VALVE_OCD_3 : 1; //5 bool F2_DISPENSER_VALVE_OCD_2 : 1; //6 bool F2_DISPENSER_VALVE_OCD_1 : 1; //7 ///Dispenser Valves Busy bool Valve_busy_7 : 1; //8 bool Valve_busy_6 : 1; //9 bool Valve_busy_5 : 1; //10 bool Valve_busy_4 : 1; //11 bool Valve_busy_3 : 1; //12 bool Valve_busy_2 : 1; //13 bool Valve_busy_1 : 1; //14 bool Valve_busy_0 : 1; //15 }bits; unsigned short ushort; }VALVE_BUSY_REG; //---------------------------------- Limit_Switches ------------------------------------------------ /* //F1_GPI_LS1_D typedef union { struct { bool F1_LS_DRYER_SPARE4 : 1; //0 bool F1_LS_DRYER_SPARE3 : 1; //1 bool F1_LS_DRYER_SPARE2 : 1; //2 bool F1_LS_DRYER_SPARE1 : 1; //3 bool F1_LS_DRYER_LID_OPEN : 1; //4 bool F1_LS_DRYER_LID_CLOSED : 1; //5 bool F1_LS_DH_SPARE2 : 1; //6 bool F1_LS_DH_LID_OPEN : 1; //7 bool F1_LS_DH_LID_CLOSED : 1; //8 bool F1_LS_DH_LID_CLEANING : 1; //9 bool F1_LS_DH_CLEAN_UP : 1; //10 bool F1_LS_DH_CLEAN_RIGHT : 1; //11 bool F1_LS_DH_CLEAN_LEFT : 1; //12 bool F1_LS_DH_CLEAN_DOWN : 1; //13 bool RESERVE_BIT14 : 1; //14 bool RESERVE_BIT15 : 1; //15 }bits; unsigned short ushort; }Limit_Switch1_REG; //F1_GPI_LS2_D typedef union { struct { bool F1_LS_PIVOT_SPARE2 : 1; //0 bool F1_LS_PIVOT_SPARE1 : 1; //1 bool F1_LS_LSPARE2 : 1; //2 bool F1_LS_LSPARE1 : 1; //3 bool F1_LS_LPIVOT_UP : 1; //4 bool F1_LS_LPIVOT_DOWN : 1; //5 bool F1_LS_LOADARM_RIGHT : 1; //6 bool F1_LS_LOADARM_LEFT : 1; //7 bool F1_LS_LLOADMOTOR_UP : 1; //8 bool F1_LS_LLOADMOTOR_DOW: 1; //9 bool F1_LS_LDANCER2_UP : 1; //10 bool F1_LS_LDANCER2_DOWN : 1; //11 bool F1_LS_LDANCER1_UP : 1; //12 bool F1_LS_LDANCER1_DOWN : 1; //13 bool RESERVE_BIT14 : 1; //14 bool RESERVE_BIT15 : 1; //15 }bits; unsigned short ushort; }Limit_Switch2_REG; //F1_GPI_LS3_D typedef union { struct { bool F1_LS_SCREW_RIGHT : 1; //0 bool F1_LS_SCREW_LEFT : 1; //1 bool F1_LS_RSPARE2 : 1; //2 bool F1_LS_RSPARE1 : 1; //3 bool F1_LS_RLOADRAM_UP : 1; //4 bool F1_LS_RDANCER_LONG : 1; //5 (F1_LS_RLOADRAM_DOWN) bool F1_LS_RLOADMOTOR_UP : 1; //6 bool F1_LS_RLOADMOTOR_DOWN : 1; //7 bool F1_LS_RDANCER_UP : 1; //8 bool F1_LS_RDANCER_DOWN : 1; //9 bool F1_SW_SPARE : 1; //10 bool F1_SW_SPOOL_EXISTS : 1; //11 bool RESERVE_BIT12 : 1; //12 bool RESERVE_BIT13 : 1; //13 bool RESERVE_BIT14 : 1; //14 bool RESERVE_BIT15 : 1; //15 }bits; unsigned short ushort; }Limit_Switch3_REG; */ //------------------------------------ SSR ---------------------------------------- /* updated 10-04-2019 # SSR TYPE USE ----------------------------------------- 1 SSR1 AC Dryer Heater Zone-1 2 SSR2 AC Dryer Heaters Zone-2 3 SSR3 DC Cleaner Pump (Ready for field upgrade) 4 SSR4 DC Mixer Chip Heater 5 SSR5 DC Dye Head Heaters Zone-4 6 SSR6 DC Dye Head Heaters Zone-3 7 SSR7 DC Dye Head Heaters Zone-2 8 SSR8 DC Dye Head Heaters Zone-1 9 SSR9 DC WHS DX Cooler 10 SSR10 DC Dye Head Heaters Zone-5 11 SSR11 DC Dye Head Heaters Zone-6 12 SSR12 DC ------------ 13 SSR13 DC Dye Head Electromagnet */ //F2_CTRL #define SPARE_SSR13_CTRL BIT0 #define SPARE_SSR12_CTRL BIT1 #define CHILLER_SSR9_CTRL BIT2 #define DYEINGH_SSR8_CTRL BIT3 #define DYEINGH_SSR7_CTRL BIT4 #define DYEINGH_SSR6_CTRL BIT5 #define DYEINGH_SSR5_CTRL BIT6 #define MIXCHIP_SSR4_CTRL BIT7 #define CLEANER_PUMP_SSR3_CTRL BIT8 //DRYER_SSR3_CTRL #define DRYER_SSR2_CTRL BIT9 #define DRYER_SSR1_CTRL BIT10 #define PDOWN_RL1_CTRL BIT11 #define RESERVE_BIT12 BIT12 #define RESERVE_BIT13 BIT13 #define RESERVE_BIT14 BIT14 #define RESERVE_BIT15 BIT15 //F1_gpo_01 #define DYEINGH_SSR10_CTRL BIT2 //HeadHeaterZ5 //F3_GPO_01_bus #define DYEINGH_SSR11_CTRL BIT4 //HeadHeaterZ6 //F2_CTRL typedef union { struct { bool F2_GPO_SPARE_SSR13_CTRL : 1; //0 bool F2_GPO_SPARE_SSR12_CTRL : 1; //1 bool F2_GPO_CHILLER_SSR9_CTRL : 1; //2 bool F2_GPO_DYEINGH_SSR8_CTRL : 1; //3 bool F2_GPO_DYEINGH_SSR7_CTRL : 1; //4 bool F2_GPO_DYEINGH_SSR6_CTRL : 1; //5 bool F2_GPO_DYEINGH_SSR5_CTRL : 1; //6 bool F2_GPO_MIXCHIP_SSR4_CTRL : 1; //7 bool F2_GPO_CLEANER_PUMP_SSR3_CTRL : 1; //8 F2_GPO_DRYER_SSR3_CTRL bool F2_GPO_DRYER_SSR2_CTRL : 1; //9 bool F2_GPO_DRYER_SSR1_CTRL : 1; //10 bool F2_GPO_PDOWN_RL1_CTRL : 1; //11 bool F2_GPO_RESERVE_BIT12 : 1; //12 bool F2_GPO_RESERVE_BIT13 : 1; //13 bool F2_GPO_RESERVE_BIT14 : 1; //14 bool F2_GPO_RESERVE_BIT15 : 1; //15 }bits; unsigned short ushort; }F2_CTRL_REG; F2_CTRL_REG F2_CTRL_Reg; //-------------------------------------------------------------------------------- //F1_LS_01_Direct typedef union { struct { bool F1_LS_DRYER_SPARE4 : 1; //0 bool F1_LS_DRYER_SPARE3 : 1; //1 bool F1_LS_DRYER_SPARE2 : 1; //2 bool F1_LS_DRYER_SPARE1 : 1; //3 bool F1_LS_DRYER_LID_OPEN : 1; //4 bool F1_LS_DRYER_LID_CLOSED : 1; //5 bool F1_LS_DH_SPARE2 : 1; //6 bool F1_LS_DH_LID_OPEN : 1; //7 bool F1_LS_DH_LID_CLOSED : 1; //8 bool F1_LS_DH_LID_CLEANING : 1; //9 bool F1_LS_DH_CLEAN_UP : 1; //10 bool F1_LS_DH_CLEAN_RIGHT : 1; //11 bool F1_LS_DH_CLEAN_LEFT : 1; //12 bool F1_LS_DH_CLEAN_DOWN : 1; //13 unsigned char RESERVE : 2; //14-15 }bits; unsigned short ushort; }LS_DRYER_DH; //F1_LS_02_Direct typedef union { struct { bool F1_LS_PIVOT_SPARE2 : 1; //0 bool F1_LS_PIVOT_SPARE1 : 1; //1 bool F1_LS_LSPARE2 : 1; //2 bool F1_LS_LSPARE1 : 1; //3 bool F1_LS_LPIVOT_UP : 1; //4 bool F1_LS_LPIVOT_DOWN : 1; //5 bool F1_DR_DOOR_SW_NO : 1; //6 F1_LS_LOADARM_RIGHT bool F1_LS_LOADARM_LEFT : 1; //7 bool F1_LS_LLOADMOTOR_UP : 1; //8 bool F1_LS_LLOADMOTOR_DOWN : 1; //9 bool F1_LS_LDANCER2_UP : 1; //10 bool F1_LS_LDANCER2_DOWN : 1; //11 bool F1_LS_LDANCER1_UP : 1; //12 bool F1_LS_LDANCER1_DOWN : 1; //13 unsigned char RESERVE : 2; //14-15 }bits; unsigned short ushort; }LS_LEFT; //F1_LS_03_Direct typedef union { struct { bool F1_LS_SCREW_RIGHT : 1; //0 bool F1_LS_SCREW_LEFT : 1; //1 bool F1_LS_RSPARE2 : 1; //2 bool F1_LS_RSPARE1 : 1; //3 bool F1_LS_RLOADRAM_UP : 1; //4 bool F1_LS_RDANCER_LONG : 1; //5 // F1_LS_RLOADRAM_DOWN bool F1_LS_RLOADMOTOR_UP : 1; //6 bool F1_LS_RLOADMOTOR_DOWN : 1; //7 bool F1_LS_RDANCER_UP : 1; //8 bool F1_LS_RDANCER_DOWN : 1; //9 bool F1_SW_SPARE : 1; //10 bool F1_SW_SPOOL_EXISTS : 1; //11 unsigned char RESERVE : 4; //12-15 }bits; unsigned short ushort; }LS_RIGHT_SCREW_SPOOL; //F2_LS_01_Direct typedef union { struct { bool F2_DISP_SAFETY_STOP_IND_1 : 1; //0 //F2_LS_DISPENSER_SPARE_1 bool F2_LS_DISPENSER_50_1 : 1; //1 bool F2_LS_DISPENSER_DOWN_1 : 1; //2 bool F2_LS_DISPENSER_75_1 : 1; //3 bool F2_LS_DISPENSER_25_1 : 1; //4 bool F2_LS_DISPENSER_UP_1 : 1; //5 bool F2_DISP_SAFETY_STOP_IND_2 : 1; //6 //F2_LS_DISPENSER_SPARE_2 bool F2_LS_DISPENSER_50_2 : 1; //7 bool F2_LS_DISPENSER_DOWN_2 : 1; //8 bool F2_LS_DISPENSER_75_2 : 1; //9 bool F2_LS_DISPENSER_25_2 : 1; //10 bool F2_LS_DISPENSER_UP_2 : 1; //11 unsigned char RESERVE : 4; //12-15 }bits; unsigned short ushort; }LS_DISPENSER_1_2; //F2_LS_02_Direct typedef union { struct { bool F2_DISP_SAFETY_STOP_IND_3 : 1; //0 //F2_LS_DISPENSER_SPARE_3 bool F2_LS_DISPENSER_50_3 : 1; //1 bool F2_LS_DISPENSER_DOWN_3 : 1; //2 bool F2_LS_DISPENSER_75_3 : 1; //3 bool F2_LS_DISPENSER_25_3 : 1; //4 bool F2_LS_DISPENSER_UP_3 : 1; //5 bool F2_DISP_SAFETY_STOP_IND_4 : 1; //6 //F2_LS_DISPENSER_SPARE_4 bool F2_LS_DISPENSER_50_4 : 1; //7 bool F2_LS_DISPENSER_DOWN_4 : 1; //8 bool F2_LS_DISPENSER_75_4 : 1; //9 bool F2_LS_DISPENSER_25_4 : 1; //10 bool F2_LS_DISPENSER_UP_4 : 1; //11 unsigned char RESERVE : 4; //12-15 }bits; unsigned short ushort; }LS_DISPENSER_3_4; //F2_LS_03_Direct typedef union { struct { bool F2_DISP_SAFETY_STOP_IND_5 : 1; //0 //F2_LS_DISPENSER_SPARE_5 bool F2_LS_DISPENSER_50_5 : 1; //1 bool F2_LS_DISPENSER_DOWN_5 : 1; //2 bool F2_LS_DISPENSER_75_5 : 1; //3 bool F2_LS_DISPENSER_25_5 : 1; //4 bool F2_LS_DISPENSER_UP_5 : 1; //5 bool F2_DISP_SAFETY_STOP_IND_6 : 1; //6 //F2_LS_DISPENSER_SPARE_6 bool F2_LS_DISPENSER_50_6 : 1; //7 bool F2_LS_DISPENSER_DOWN_6 : 1; //8 bool F2_LS_DISPENSER_75_6 : 1; //9 bool F2_LS_DISPENSER_25_6 : 1; //10 bool F2_LS_DISPENSER_UP_6 : 1; //11 unsigned char RESERVE : 4; //12-15 }bits; unsigned short ushort; }LS_DISPENSER_5_6; //F2_LS_04_Direct typedef union { struct { bool F2_DISP_SAFETY_STOP_IND_7 : 1; //0 //F2_LS_DISPENSER_SPARE_7 bool F2_LS_DISPENSER_50_7 : 1; //1 bool F2_LS_DISPENSER_DOWN_7 : 1; //2 bool F2_LS_DISPENSER_75_7 : 1; //3 bool F2_LS_DISPENSER_25_7 : 1; //4 bool F2_LS_DISPENSER_UP_7 : 1; //5 bool F2_DISP_SAFETY_STOP_IND_8 : 1; //6 //F2_LS_DISPENSER_SPARE_8 bool F2_LS_DISPENSER_50_8 : 1; //7 bool F2_LS_DISPENSER_DOWN_8 : 1; //8 bool F2_LS_DISPENSER_75_8 : 1; //9 bool F2_LS_DISPENSER_25_8 : 1; //10 bool F2_LS_DISPENSER_UP_8 : 1; //11 unsigned char RESERVE : 4; //12-15 }bits; unsigned short ushort; }LS_DISPENSER_7_8; //F1_GPI_EXTWINDER_D typedef union { struct { bool F1_GPI_EXTWINDER_3 : 1; //0 bool F1_GPI_EXTWINDER_2 : 1; //1 bool F1_GPI_EXTWINDER_1 : 1; //2 bool F1_GPI_TFEED_BREAK_2 : 1; //3 bool F1_GPI_TFEED_BREAK_1 : 1; //4 unsigned short RESERVE : 11; //5-15 }bits; unsigned short ushort; }GPI_EXTWINDER_TFEED_BREAK; //------------------------------ MOTOR DRIVER L_6470 ------------------------------ typedef union { struct { unsigned short LSB; unsigned short MSB; }ushort; unsigned int uint; }INT2SHORT;//16->32 typedef union { struct { unsigned char LSB; unsigned char MSB; }uchar; unsigned short uint; }SHORT2CHAR;//16->8 typedef union { struct { unsigned char UCHAR_0; unsigned char UCHAR_1; unsigned char UCHAR_2; unsigned char UCHAR_3; }uchar; unsigned int uint; }INT2CHAR;//32->8 //enum //{ // RLOADING, // RDRIVING, // F1_LDRIVING, // F1_LLOADING, // F1_DRYER_LOADARM, // F1_DRYER_DRIVING, // F1_DH_CLEANHEAD, // F1_DH_CLEANMECH, // F1_SCREW, // F1_WINDER, // RLOADARM, // RDANCER, // LDANCER1, // LDANCER2, // DRYER_LID, // DH_LID, // LPIVOT1, //}SPI_TYPE; ////SPI //typedef struct //S_SPI //{ // unsigned char Type; // unsigned int TX_MOSI; //32bit (Master Output Slave Input ) // unsigned int RX_MISO; //24bit (Master Input Slave Output) // //unsigned int BUSY; //32bit // //}SPI;//SPI /* #define L6470_MOSI (*((volatile short *)(BASE | 0x0100))) #define L6470_MISO (*((volatile short *)(BASE | 0x0200))) #define L6470_CS (*((volatile short *)(BASE | 0x0300))) #define L6470_CLK (*((volatile short *)(BASE | 0x0400))) #define L6470_BUSY (*((volatile short *)(BASE | 0x0500))) #define L6470_RESET (*((volatile short *)(BASE | 0x0600))) #define L6470_TX (*((volatile char *)(BASE | 0x0700))) #define L6470_RX (*((volatile char *)(BASE | 0x0800))) */ // ------------ WHS ---------------------- //F2_GPI_REGISTER1_Direct typedef union { struct { bool F2_WASTE_OVERFULL_NO : 1; //0 F2_GPI_CHILLER_STAT1 bool F2_GPI_CHILLER_FAULT : 1; //1 bool F2_WASTE_FLOW_SW_NO : 1; //2 F2_GPI_AIRFLOW_FLAP unsigned short RESERVE :13; //3-15 }bits; unsigned short ushort; }F2_GPI_REG; //F3_GPI_01_D typedef union { struct { bool F3_GPI_WCONTAINER_WARN : 1; //0 bool F3_GPI_WCONTAINER_FULL : 1; //1 bool F3_GPI_SW_FILTER_PRES : 1; //2 FILTER_PRES_SW_NO bool F3_GPI_PANSW6 : 1; //3 bool F3_GPI_PANSW5 : 1; //4 bool F3_GPI_PANSW4 : 1; //5 bool F3_GPI_PANSW3 : 1; //6 bool F3_GPI_PANSW2 : 1; //7 bool F3_GPI_PANSW1 : 1; //8 bool F3_MON_5V_IF : 1; //9 if voltage at least 90% of the power = "1" else "0" bool F3_MON_5V_RS : 1; //10 bool F3_MON_3V3_IF : 1; //11 bool F3_MON_5V_BP : 1; //12 unsigned char RESERVE : 3; //13-15 }bits; unsigned short ushort; }F3_GPI_01; //F1_GPO_02_bus typedef union { struct { bool F1_RFID_CART1_RST : 1; //0 F1_FAN1_PWMCTRL bool F1_RFID_CART2_RST : 1; //1 F1_FAN2_PWMCTRL bool F1_RFID_CART3_RST : 1; //2 F1_FAN3_PWMCTRL bool F1_FAN4_PWMCTRL : 1; //3 bool F1_FAN5_PWMCTRL : 1; //4 unsigned short RESERVE :11; //5-15 }bits; unsigned short ushort; }F1_GPO_REG2; //F3_MIDTANK_02_Direct , F3_MIDTANK_02_Latched typedef union { struct { bool F3_MIDTANK4_LVL4_FLOAT_2 : 1; //0 NA bool F3_MIDTANK4_LVL4_FLOAT_1 : 1; //1 NA bool F3_RFID_CART3_INT : 1; //2 F3_MIDTANK4_LVL3_FLOAT_2 bool F3_MIDTANK4_LVL3_FLOAT_1 : 1; //3 NA bool F3_MIDTANK4_LVL2_FLOAT_2 : 1; //4 NA bool F3_MIDTANK4_LVL2_FLOAT_1 : 1; //5 NA bool F3_RFID_CART2_INT : 1; //6 F3_MIDTANK4_LVL1_FLOAT_2 bool F3_MIDTANK4_LVL1_FLOAT_1 : 1; //7 NA bool F3_MIDTANK3_LVL4_FLOAT_2 : 1; //8 NA bool F3_MIDTANK3_LVL4_FLOAT_1 : 1; //9 NA bool F3_RFID_CART1_INT : 1; //10 F3_MIDTANK3_LVL3_FLOAT_2 bool F3_MIDTANK3_LVL3_FLOAT_1 : 1; //11 NA bool F3_MIDTANK3_LVL2_FLOAT_2 : 1; //12 NA bool F3_MIDTANK3_LVL2_FLOAT_1 : 1; //13 NA bool F3_MIDTANK3_LVL1_FLOAT_2 : 1; //14 NA bool F3_MIDTANK3_LVL1_FLOAT_1 : 1; //15 NA }bits; unsigned short ushort; }F3_GPI_Interrupt; // ---------------------------------- //F1_Moto_Driver_SPI_DIRECTION1 typedef union { struct { bool F1_MOTO_LPIVOT1 : 1; //0 bool F1_MOTO_LLOADING : 1; //1 bool F1_MOTO_LDRIVING : 1; //2 bool F1_MOTO_LDANCER2 : 1; //3 bool F1_MOTO_LDANCER1 : 1; //4 bool F1_MOTO_DRYER_LOADARM : 1; //5 bool F1_MOTO_DRYER_LID : 1; //6 bool F1_MOTO_DRYER_DRIVING : 1; //7 bool F1_MOTO_DH_LID : 1; //8 bool F1_MOTO_DH_CLEANMECH : 1; //9 bool F1_MOTO_DH_CLEANHEAD : 1; //10 unsigned char RESERVE1 : 5; //11-15 }bits; unsigned short ushort; }F1_SPI_DIRECTION1; //F1_Moto_Driver_SPI_DIRECTION2 typedef union { struct { bool F1_MOTO_WINDER : 1; //0 bool F1_MOTO_SCREW : 1; //1 bool F1_MOTO_RLOADING : 1; //2 bool F1_MOTO_RLOADARM : 1; //3 bool F1_MOTO_RDRIVING : 1; //4 bool F1_MOTO_RDANCER : 1; //5 unsigned short RESERVE1 : 10;//6-15 }bits; unsigned short ushort; }F1_SPI_DIRECTION2; //F2_Moto_Driver_SPI_DIRECTION1 typedef union { struct { bool F2_MOTO_DISPENSER_8 : 1; //0 bool F2_MOTO_DISPENSER_7 : 1; //1 bool F2_MOTO_DISPENSER_6 : 1; //2 bool F2_MOTO_DISPENSER_5 : 1; //3 bool F2_MOTO_DISPENSER_4 : 1; //4 bool F2_MOTO_DISPENSER_3 : 1; //5 bool F2_MOTO_DISPENSER_2 : 1; //6 bool F2_MOTO_DISPENSER_1 : 1; //7 unsigned char RESERVE1 : 8; //8-15 }bits; unsigned short ushort; }F2_SPI_DIRECTION1; //F3_Moto_Driver_SPI_DIRECTION1 typedef union { struct { bool F3_MOTO_SPARE3_1 : 1; //0 bool F3_MOTO_SPARE2_2 : 1; //1 bool F3_MOTO_SPARE2_1 : 1; //2 bool F3_MOTO_SPARE1_2 : 1; //3 bool F3_MOTO_SPARE1_1 : 1; //4 unsigned short RESERVE1 : 10;//5-15 }bits; unsigned short ushort; }F3_SPI_DIRECTION1; //F3_MOTO_CLK_SRC_SEL typedef union { struct { bool RDRIVING : 1; //0 (MOTO_CLK1_2) bool LDRIVING : 1; //1 (MOTO_CLK2_1) bool SCREW : 1; //2 (MOTO_CLK5_1) bool WINDER : 1; //3 (MOTO_CLK5_2) uint16_t RESERVE : 12; //4-16 }Motor; unsigned short ushort; }F3MotoClkSrcSel; F3MotoClkSrcSel F3_Moto_Clk_Src_Sel; //L6470_MOSI = 0x00; #endif /* DRIVERS_FPGA_FPGA_COMM_H_ */