blob: 0a2ff5a9897ccdbf08fbf29c2a96df00762fb9cf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
|
#include <DataDef.h>
#include <stdbool.h>
#include <stdlib.h>
#include <stdint.h>
#include "driverlib/epi.h"
#include "inc/hw_memmap.h"
#include "FPGA_COMM.h"
#include "driverlib/sysctl.h" //for SysCtlDelay
unsigned short GPO_01_Reg;
int test_FPGA()
{
GP_Out_01 Gpo_01;
Gpo_01.bits.F3_GPO_LED4 = 1;
Gpo_01.bits.F3_GPO_LED3 = 1;
Gpo_01.bits.F3_GPO_LED2 = 0;
Gpo_01.bits.F3_GPO_LED1 = 1;
Gpo_01.bits.F3_GPO_EXTWINDER_SSR11_CTRL = 1;
Gpo_01.bits.F3_GPO_BUZZER = 0;
Gpo_01.bits.F3_SPARE2_ROTENC_CLK = 1;
Gpo_01.bits.F3_SPARE1_ROTENC_CLK = 1;
Gpo_01.bits.RESERVE = 0xF5;
GPO_01_Reg = Gpo_01.ushort;
return 0;
}
int Test_FPGA_ReadBack(unsigned char FPGA_NUM, unsigned short Value, unsigned short *ReadBackValue)// = 0x1234)
{
//TODO to update the deley
if(FPGA_NUM == 1)
{
F1_Test = Value;
SysCtlDelay(100);
*ReadBackValue = F1_Test;
if(Value == !F1_Test)
return PASSED;
}
if(FPGA_NUM == 2)
{
F2_Test = Value;
SysCtlDelay(100);
*ReadBackValue = F2_Test;
if(Value == !F2_Test)
return PASSED;
}
if(FPGA_NUM == 3)
{
F3_Test = Value;
SysCtlDelay(100);
*ReadBackValue = F3_Test;
if(Value == !F3_Test)
return PASSED;
}
return FAILED;
}
int FPGA_ReadVersion(unsigned char FPGA_NUM, unsigned char *Version, unsigned char *Year, unsigned char *Month, unsigned char *Day)
{
VER1 Ver1;
VER2 Ver2;
switch(FPGA_NUM)
{
case 1:
Ver1.ushort = F1_Ver1_D;
Ver2.ushort = F1_Ver2_D;
break;
case 2:
Ver1.ushort = F2_Ver1_D;
Ver2.ushort = F2_Ver2_D;
break;
case 3:
Ver1.ushort = F3_Ver1_D;
Ver2.ushort = F3_Ver2_D;
break;
default:
break;
}
if( (Ver1.bytes.Month > 12) || (Ver1.bytes.Day > 31) || (Ver2.bytes.Year < 17) )
{
return FAILED;
}
*Month = Ver1.bytes.Month;
*Day = Ver1.bytes.Day;
*Year = Ver2.bytes.Year; // to check how many digits is needed
*Version = Ver2.bytes.Ver_num;
return PASSED;
}
void Init_FPGA()
{
//PreScale + PWM
//60MHz / PreScaler / (PWM High + PWM Low)
//for SPI Motor driver the maximum is 5MHz the default is the FPGA is 4 (60/2/(2+3)) = 4
//EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3)
// Value Description
// 0x0 Active WRn is 2 EPI clocks
// 0x1 Active WRn is 4 EPI clocks <--
// 0x2 Active WRn is 6 EPI clocks
// 0x3 Active WRn is 8 EPI clocks
#ifndef EVALUATION_BOARD
EPIModeSet(EPI0_BASE, EPI_MODE_HB16);
EPIConfigHB16Set(EPI0_BASE, EPI_HB16_MODE_ADMUX | EPI_HB16_WRWAIT_1 | EPI_HB16_RDWAIT_1 | EPI_HB16_ALE_LOW | EPI_HB16_WORD_ACCESS, 0);
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_BASE_6 | EPI_ADDR_RAM_SIZE_64KB);
#endif
}
|
