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#include "include.h"
#include <DataDef.h>
#include <stdbool.h>
#include <stdlib.h>
#include <stdint.h>
#include "driverlib/epi.h"
#include "inc/hw_memmap.h"
#include "FPGA_COMM.h"
#include "driverlib/sysctl.h" //for SysCtlDelay
#include <driverlib/sysctl.h>
#include "Drivers/Peripheral_GPIO/GPIO.h"
unsigned short GPO_01_Reg;
int FPGA_Test()
{
GP_Out_01 Gpo_01;
Gpo_01.bits.F3_GPO_LED4 = 1;
Gpo_01.bits.F3_GPO_LED3 = 1;
Gpo_01.bits.F3_GPO_LED2 = 0;
Gpo_01.bits.F3_GPO_LED1 = 1;
Gpo_01.bits.F3_GPO_EXTWINDER_SSR11_CTRL = 1;
Gpo_01.bits.F3_GPO_BUZZER = 0;
Gpo_01.bits.F3_SPARE2_ROTENC_CLK = 1;
Gpo_01.bits.F3_SPARE1_ROTENC_CLK = 1;
Gpo_01.bits.RESERVE = 0xF5;
GPO_01_Reg = Gpo_01.ushort;
return 0;
}
int FPGA_Test_ReadBack(unsigned char FPGA_NUM, unsigned short Value, unsigned short *ReadBackValue)// = 0x1234)
{
//TODO to update the deley
unsigned short readValue = 0;
if(FPGA_NUM == 1)
{
F1_Test = Value;
SysCtlDelay(1000);
readValue = F1_Test;
*ReadBackValue = readValue;
if(Value == (uint16_t) ~((unsigned int) readValue))
return PASSED;
if((Value == 0xFFFF) && (readValue == 0))
return PASSED;
}
if(FPGA_NUM == 2)
{
F2_Test = Value;
SysCtlDelay(100);
readValue = F2_Test;
*ReadBackValue = readValue;
if(Value == (uint16_t) ~((unsigned int) readValue))
return PASSED;
if((Value == 0xFFFF) && (readValue == 0))
return PASSED;
}
if(FPGA_NUM == 3)
{
F3_Test = Value;
SysCtlDelay(100);
readValue = F3_Test;
*ReadBackValue = readValue;
if(Value == (uint16_t) ~((unsigned int) readValue))
return PASSED;
if((Value == 0xFFFF) && (readValue == 0))
return PASSED;
}
return FAILED;
}
int FPGA_ReadVersion(unsigned char FPGA_NUM, unsigned char *Version, unsigned char *Year, unsigned char *Month, unsigned char *Day)
{
VER1 Ver1;
VER2 Ver2;
switch(FPGA_NUM)
{
case 1:
Ver1.ushort = F1_Ver1_D;
Ver2.ushort = F1_Ver2_D;
break;
case 2:
Ver1.ushort = F2_Ver1_D;
Ver2.ushort = F2_Ver2_D;
break;
case 3:
Ver1.ushort = F3_Ver1_D;
Ver2.ushort = F3_Ver2_D;
break;
default:
break;
}
/* if( (Ver1.bytes.Month > 12) || (Ver1.bytes.Day > 31) || (Ver2.bytes.Year < 17) )
{
return FAILED;
}
*/
*Month = Ver1.bytes.Month;
*Day = Ver1.bytes.Day;
*Year = Ver2.bytes.Year; // to check how many digits is needed
*Version = Ver2.bytes.Ver_num;
return PASSED;
}
void FPGA_Init()
{
#ifndef EVALUATION_BOARD
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_6); // start FPGA (clear HW RESET)
ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_6, GPIO_PIN_6);
// Enable EPI
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
while (!(SysCtlPeripheralReady(SYSCTL_PERIPH_EPI0)));
//PreScale + PWM
//60MHz / PreScaler / (PWM High + PWM Low)
//for SPI Motor driver the maximum is 5MHz the default is the FPGA is 4 (60/2/(2+3)) = 4
//EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3)
// Value Description
// 0x0 Active WRn is 2 EPI clocks
// 0x1 Active WRn is 4 EPI clocks <--
// 0x2 Active WRn is 6 EPI clocks
// 0x3 Active WRn is 8 EPI clocks
// EPIModeSet(EPI0_BASE, EPI_MODE_HB16);
// EPIConfigHB16Set(EPI0_BASE, EPI_HB16_MODE_ADMUX | EPI_HB16_WRWAIT_1 | EPI_HB16_RDWAIT_1 | EPI_HB16_ALE_LOW | EPI_HB16_WORD_ACCESS, 0);
// EPIConfigHB16Set(EPI0_BASE, EPI_HB16_WRWAIT_1 | EPI_HB16_RDWAIT_1, 0);
EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);
//uint32_t temp = *(uint32_t)(EPI0_BASE+0x10);
// volatile uint32_t *temp;
// temp = (volatile uint32_t *) (EPI0_BASE+0x10);
// Set EPI Mode
EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_CLKPIN |EPI_GPMODE_FRAME50 | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_DSIZE_16, 4, 0);
//Set EPI CLK
EPIDividerSet(EPI0_BASE, 10);//60MHz
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_BASE_6 | EPI_ADDR_RAM_SIZE_64KB);
// *temp |= 0x50;
//FPGA_WRITE();
#endif
}
//---------------------------------- Limit_Switches ------------------------------------------------
Limit_Switch1_REG Limit_Switch1;
Limit_Switch2_REG Limit_Switch2;
Limit_Switch3_REG Limit_Switch3;
void FPGA_Read_limit_Switches()
{
Limit_Switch1.ushort = F1_GPI_LS1_D;
Limit_Switch2.ushort = F1_GPI_LS2_D;
Limit_Switch3.ushort = F1_GPI_LS3_D;
}
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