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<mahapps:MetroWindow x:Class="Tango.MachineStudio.UI.MainWindow"
        xmlns="http://schemas.microsoft.com/winfx/2006/xaml/presentation"
        xmlns:x="http://schemas.microsoft.com/winfx/2006/xaml"
        xmlns:d="http://schemas.microsoft.com/expression/blend/2008"
        xmlns:mahapps="http://metro.mahapps.com/winfx/xaml/controls"
        xmlns:mc="http://schemas.openxmlformats.org/markup-compatibility/2006"
        xmlns:local="clr-namespace:Tango.MachineStudio.UI"
        xmlns:views="clr-namespace:Tango.MachineStudio.UI.Views"
        xmlns:sharedControls="clr-namespace:Tango.SharedUI.Controls;assembly=Tango.SharedUI"
        mc:Ignorable="d"
        Title="Tango" Height="800" Width="1280"  Foreground="{StaticResource MainWindow.Foreground}" FontFamily="{StaticResource flexo}" 
                     BorderThickness="1"  BorderBrush="{StaticResource AccentColorBrush}" Background="{DynamicResource MainWindow.Background}" WindowTitleBrush="{StaticResource MainWindow.WindowTitleColorBrush}">

    <Grid x:Name="main_grid">
        <Grid.Background>
            <ImageBrush ImageSource="/Images/White-Abstract.png" Stretch="Fill"></ImageBrush>
        </Grid.Background>
        <!--<Viewbox Stretch="Fill" x:Name="viewbox">-->
            <Grid x:Name="grid" Width="1920" Height="1145">
                <Grid>
                    <sharedControls:NavigationControl TransitionAlwaysFades="True" TransitionType="Zoom" x:Name="NavigationControl" x:FieldModifier="public">
                        <views:LoadingView sharedControls:NavigationControl.NavigationName="LoadingView"></views:LoadingView>
                        <views:LoginView sharedControls:NavigationControl.NavigationName="LoginView"></views:LoginView>
                        <views:MainView sharedControls:NavigationControl.NavigationName="MainView"></views:MainView>
                        <views:ShutdownView sharedControls:NavigationControl.NavigationName="ShutdownView"></views:ShutdownView>
                        <views:UpdateView sharedControls:NavigationControl.NavigationName="UpdateView"></views:UpdateView>
                    </sharedControls:NavigationControl>

                    <Grid Background="Black" Opacity="0.7" x:Name="shadowGrid" Visibility="Hidden">

                    </Grid>
                </Grid>
            </Grid>
        <!--</Viewbox>-->
    </Grid>
</mahapps:MetroWindow>
#include <stdbool.h>

//Address is = 16 Bit :  4bit_base , 3bit_fpga_base , 9bit_Address (Word1OrByte2)
//Base Address 0X000

#define BASE                 0x08 << 12 //TODO
#define FPGA1_BASE  (BASE | (0x00 << 0x09))
#define FPGA2_BASE  (BASE | (0x01 << 0x09))
#define FPGA3_BASE  (BASE | (0x02 << 0x09))

//TODO update the addresses Word1OrByte2 !!!
#define Word1OrByte2 0x01//0x01 for Word, 0x02 for Byte

//Registers definitions

// * * * * * * * * * * * * * * * * FPGA 1  * * * * * * * * * * * * * * * * //

//Version1
#define F1_Ver1_D                              (*((volatile short  *)(FPGA1_BASE | (0x0 * Word1OrByte2))))  //Version of Fpga is held here

//Version2
#define F1_Ver2_D                              (*((volatile short  *)(FPGA1_BASE | (0x8 * Word1OrByte2))))  //Version of Fpga is held here

//GPI shorterrupt LS_01 Registers
#define F1_GPI_LS1_D                           (*((volatile short  *)(FPGA1_BASE | (0x10 * Word1OrByte2))))    //Reads the direct values that are currently being sent to the fpga.
#define F1_GPI_LS1_L                           (*((volatile short  *)(FPGA1_BASE | (0x11 * Word1OrByte2))))    //Value of the latched shorterrupts that have occurred
#define F1_GPI_LS1_M                           (*((volatile short  *)(FPGA1_BASE | (0x12 * Word1OrByte2))))    //Value of the shorterrupt mask, Default is 0x0000

//GPI shorterrupt LS_02 Registers
#define F1_GPI_LS2_D                           (*((volatile short  *)(FPGA1_BASE | (0x18 * Word1OrByte2))))    //Reads the direct values that are currently being sent to the fpga.
#define F1_GPI_LS2_L                           (*((volatile short  *)(FPGA1_BASE | (0x19 * Word1OrByte2))))    //Value of the latched shorterrupts that have occurred
#define F1_GPI_LS2_M                           (*((volatile short  *)(FPGA1_BASE | (0x1a * Word1OrByte2))))    //Value of the shorterrupt mask, Default is 0x0000

//GPI shorterrupt LS_03 Registers
#define F1_GPI_LS3_D                           (*((volatile short  *)(FPGA1_BASE | (0x20 * Word1OrByte2))))     //Reads the direct values that are currently being sent to the fpga.
#define F1_GPI_LS3_L                           (*((volatile short  *)(FPGA1_BASE | (0x21 * Word1OrByte2))))     //Value of the latched shorterrupts that have occurred
#define F1_GPI_LS3_M                           (*((volatile short  *)(FPGA1_BASE | (0x22 * Word1OrByte2))))     //Value of the shorterrupt mask, Default is 0x0000

//Moto_Driver_NBUSY_register1
#define F1_Moto_Driver_NBUSY1_D                (*((volatile short  *)(FPGA1_BASE | (0x28 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F1_Moto_Driver_NBUSY1_L                (*((volatile short  *)(FPGA1_BASE | (0x29 * Word1OrByte2))))   //Value of the latched shorterrupts that have occurred
#define F1_Moto_Driver_NBUSY1_M                (*((volatile short  *)(FPGA1_BASE | (0x2a * Word1OrByte2))))   //Value of the shorterrupt mask, Default is 0x0000

//Moto_Driver_NBUSY_register2
#define F1_Moto_Driver_NBUSY2_D                (*((volatile short  *)(FPGA1_BASE | (0x30 * Word1OrByte2))))  //Reads the direct values that are currently being sent to the fpga.
#define F1_Moto_Driver_NBUSY2_L                (*((volatile short  *)(FPGA1_BASE | (0x31 * Word1OrByte2))))  //Value of the latched shorterrupts that have occurred
#define F1_Moto_Driver_NBUSY2_M                (*((volatile short  *)(FPGA1_BASE | (0x32 * Word1OrByte2))))  //Value of the shorterrupt mask, Default is 0x0000

//GPI_EXTWINDER_and_TFEED_BRK
#define F1_GPI_EXTWINDER_D                     (*((volatile short  *)(FPGA1_BASE | (0x38 * Word1OrByte2))))    //Reads the direct values that are currently being sent to the fpga.
#define F1_GPI_EXTWINDER_L                     (*((volatile short  *)(FPGA1_BASE | (0x39 * Word1OrByte2))))    //Value of the latched shorterrupts that have occurred
#define F1_GPI_EXTWINDER_M                     (*((volatile short  *)(FPGA1_BASE | (0x3a * Word1OrByte2))))    //Value of the shorterrupt mask, Default is 0x0000

//SPI_Busy_register1
#define F1_SPI_Busy1_D                         (*((volatile short  *)(FPGA1_BASE | (0x048 * Word1OrByte2))))  //Reads the direct values that are currently being sent to the fpga.
#define F1_SPI_Busy1_L                         (*((volatile short  *)(FPGA1_BASE | (0x049 * Word1OrByte2))))  //Value of the latched shorterrupts that have occurred
#define F1_SPI_Busy1_M                         (*((volatile short  *)(FPGA1_BASE | (0x04a * Word1OrByte2))))  //Value of the shorterrupt mask, Default is 0x0000

//SPI_Busy_register2
#define F1_SPI_Busy2_D                         (*((volatile short  *)(FPGA1_BASE | (0x050 * Word1OrByte2))))  //Reads the direct values that are currently being sent to the fpga.
#define F1_SPI_Busy2_L                         (*((volatile short  *)(FPGA1_BASE | (0x051 * Word1OrByte2))))  //Value of the latched shorterrupts that have occurred
#define F1_SPI_Busy2_M                         (*((volatile short  *)(FPGA1_BASE | (0x052 * Word1OrByte2))))  //Value of the shorterrupt mask, Default is 0x0000

//Moto_Driver_NSTBYRST_register1
#define F1_Moto_Driver_NSTBYRST1               (*((volatile short  *)(FPGA1_BASE | (0x059 * Word1OrByte2))))   //Writes to values. Readback thevaluessthat are currently in the GPO register

//Moto_Driver_NSTBYRST_register2
#define F1_Moto_Driver_NSTBYRST2               (*((volatile short  *)(FPGA1_BASE | (0x061 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//Moto_Driver_SW_register1
#define F1_Moto_Driver_SW1                     (*((volatile short  *)(FPGA1_BASE | (0x069 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//Moto_Driver_SW_register2
#define F1_Moto_Driver_SW2                     (*((volatile short  *)(FPGA1_BASE | (0x071 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//QEI_SCREW_ROTENC
#define F1_SCREW_ROTENC_L                      (*((volatile short  *)(FPGA1_BASE | (0x080 * Word1OrByte2))))  //Value of the lsb of the QEI register
#define F1_SCREW_ROTENC_M                      (*((volatile short  *)(FPGA1_BASE | (0x081 * Word1OrByte2))))  //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F1_SCREW_ROTENC_I                      (*((volatile short  *)(FPGA1_BASE | (0x082 * Word1OrByte2))))  //value of index counter

//QEI_RSPARE_ROTENC
#define F1_RSPARE_ROTENC_L                     (*((volatile short  *)(FPGA1_BASE | (0x088 * Word1OrByte2))))  //Value of the lsb of the QEI register
#define F1_RSPARE_ROTENC_M                     (*((volatile short  *)(FPGA1_BASE | (0x089 * Word1OrByte2))))  //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F1_RSPARE_ROTENC_I                     (*((volatile short  *)(FPGA1_BASE | (0x08a * Word1OrByte2))))    //value of index counter

//QEI_LSPARE1_ROTENC
#define F1_LSPARE1_ROTENC_L                    (*((volatile short  *)(FPGA1_BASE | (0x090 * Word1OrByte2))))  //Value of the lsb of the QEI register
#define F1_LSPARE1_ROTENC_M                    (*((volatile short  *)(FPGA1_BASE | (0x091 * Word1OrByte2))))  //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F1_LSPARE1_ROTENC_I                    (*((volatile short  *)(FPGA1_BASE | (0x092 * Word1OrByte2))))    //value of index counter

//QEI_RSPEEDSENS_ROTENC
#define F1_RSPEEDSENS_ROTENC_L                 (*((volatile short  *)(FPGA1_BASE | (0x098 * Word1OrByte2))))    //Value of the lsb of the QEI register
#define F1_RSPEEDSENS_ROTENC_M                 (*((volatile short  *)(FPGA1_BASE | (0x099 * Word1OrByte2))))    //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F1_RSPEEDSENS_ROTENC_I                 (*((volatile short  *)(FPGA1_BASE | (0x09a * Word1OrByte2))))    //value of index counter

//QEI_LSPARE2_ROTENC
#define F1_LSPARE2_ROTENC_L                    (*((volatile short  *)(FPGA1_BASE | (0x0A0 * Word1OrByte2))))    //Value of the lsb of the QEI register
#define F1_LSPARE2_ROTENC_M                    (*((volatile short  *)(FPGA1_BASE | (0x0A1 * Word1OrByte2))))    //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F1_LSPARE2_ROTENC_I                    (*((volatile short  *)(FPGA1_BASE | (0x0A2 * Word1OrByte2))))      //value of index counter

//QEI_DRYER_LOADARM_ROTENC
#define F1_DRYER_LOADARM_ROTENC_L              (*((volatile short  *)(FPGA1_BASE | (0x0a8 * Word1OrByte2))))   //Value of the lsb of the QEI register
#define F1_DRYER_LOADARM_ROTENC_M              (*((volatile short  *)(FPGA1_BASE | (0x0a9 * Word1OrByte2))))   //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F1_DRYER_LOADARM_ROTENC_I              (*((volatile short  *)(FPGA1_BASE | (0x0aa * Word1OrByte2))))     //value of index counter

//SPI_MOTO_RLOADING_A1
#define F1_MOTO_RLOADING_A1_TX_00              (*((volatile short  *)(FPGA1_BASE | (0x100 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RLOADING_A1_TX_01              (*((volatile short  *)(FPGA1_BASE | (0x101 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RLOADING_A1_RX_00              (*((volatile short  *)(FPGA1_BASE | (0x102 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_RLOADING_A1_RX_01              (*((volatile short  *)(FPGA1_BASE | (0x103 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_RLOADING_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x104 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_RDRIVING_A1
#define F1_MOTO_RDRIVING_A1_TX_00              (*((volatile short  *)(FPGA1_BASE | (0x108 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RDRIVING_A1_TX_01              (*((volatile short  *)(FPGA1_BASE | (0x109 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RDRIVING_A1_RX_00              (*((volatile short  *)(FPGA1_BASE | (0x10A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_RDRIVING_A1_RX_01              (*((volatile short  *)(FPGA1_BASE | (0x10B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_RDRIVING_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x10C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_LDRIVING_A1
#define F1_MOTO_LDRIVING_A1_TX_00              (*((volatile short  *)(FPGA1_BASE | (0x110 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LDRIVING_A1_TX_01              (*((volatile short  *)(FPGA1_BASE | (0x111 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LDRIVING_A1_RX_00              (*((volatile short  *)(FPGA1_BASE | (0x112 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_LDRIVING_A1_RX_01              (*((volatile short  *)(FPGA1_BASE | (0x113 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_LDRIVING_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x114 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_LLOADING_A1
#define F1_MOTO_LLOADING_A1_TX_00              (*((volatile short  *)(FPGA1_BASE | (0x118 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LLOADING_A1_TX_01              (*((volatile short  *)(FPGA1_BASE | (0x119 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LLOADING_A1_RX_00              (*((volatile short  *)(FPGA1_BASE | (0x11A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_LLOADING_A1_RX_01              (*((volatile short  *)(FPGA1_BASE | (0x11B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_LLOADING_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x11C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_DRYER_LOADARM_A1
#define F1_MOTO_DRYER_LOADARM_A1_TX_00         (*((volatile short  *)(FPGA1_BASE | (0x120 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DRYER_LOADARM_A1_TX_01         (*((volatile short  *)(FPGA1_BASE | (0x121 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DRYER_LOADARM_A1_RX_00         (*((volatile short  *)(FPGA1_BASE | (0x122 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_DRYER_LOADARM_A1_RX_01         (*((volatile short  *)(FPGA1_BASE | (0x123 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_DRYER_LOADARM_A1_WORDS         (*((volatile short  *)(FPGA1_BASE | (0x124 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_DRYER_DRIVING_A1
#define F1_MOTO_DRYER_DRIVING_A1_TX_00         (*((volatile short  *)(FPGA1_BASE | (0x128 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DRYER_DRIVING_A1_TX_01         (*((volatile short  *)(FPGA1_BASE | (0x129 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DRYER_DRIVING_A1_RX_00         (*((volatile short  *)(FPGA1_BASE | (0x12A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_DRYER_DRIVING_A1_RX_01         (*((volatile short  *)(FPGA1_BASE | (0x12B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_DRYER_DRIVING_A1_WORDS         (*((volatile short  *)(FPGA1_BASE | (0x12C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_DH_CLEANHEAD_A1
#define F1_MOTO_DH_CLEANHEAD_A1_TX_00          (*((volatile short  *)(FPGA1_BASE | (0x130 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DH_CLEANHEAD_A1_TX_01          (*((volatile short  *)(FPGA1_BASE | (0x131 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DH_CLEANHEAD_A1_RX_00          (*((volatile short  *)(FPGA1_BASE | (0x132 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_DH_CLEANHEAD_A1_RX_01          (*((volatile short  *)(FPGA1_BASE | (0x133 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_DH_CLEANHEAD_A1_WORDS          (*((volatile short  *)(FPGA1_BASE | (0x134 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_DH_CLEANMECH_A1
#define F1_MOTO_DH_CLEANMECH_A1_TX_00          (*((volatile short  *)(FPGA1_BASE | (0x138 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DH_CLEANMECH_A1_TX_01          (*((volatile short  *)(FPGA1_BASE | (0x139 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DH_CLEANMECH_A1_RX_00          (*((volatile short  *)(FPGA1_BASE | (0x13A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_DH_CLEANMECH_A1_RX_01          (*((volatile short  *)(FPGA1_BASE | (0x13B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_DH_CLEANMECH_A1_WORDS          (*((volatile short  *)(FPGA1_BASE | (0x13C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_SCREW_A1
#define F1_MOTO_SCREW_A1_TX_00                 (*((volatile short  *)(FPGA1_BASE | (0x140 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_SCREW_A1_TX_01                 (*((volatile short  *)(FPGA1_BASE | (0x141 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_SCREW_A1_RX_00                 (*((volatile short  *)(FPGA1_BASE | (0x142 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_SCREW_A1_RX_01                 (*((volatile short  *)(FPGA1_BASE | (0x143 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_SCREW_A1_WORDS                 (*((volatile short  *)(FPGA1_BASE | (0x144 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_WINDER_A1
#define F1_MOTO_WINDER_A1_TX_00                (*((volatile short  *)(FPGA1_BASE | (0x148 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_WINDER_A1_TX_01                (*((volatile short  *)(FPGA1_BASE | (0x149 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_WINDER_A1_RX_00                (*((volatile short  *)(FPGA1_BASE | (0x14A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_WINDER_A1_RX_01                (*((volatile short  *)(FPGA1_BASE | (0x14B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_WINDER_A1_WORDS                (*((volatile short  *)(FPGA1_BASE | (0x14C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_RLOADARM_A1
#define F1_MOTO_RLOADARM_A1_TX_00              (*((volatile short  *)(FPGA1_BASE | (0x150 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RLOADARM_A1_TX_01              (*((volatile short  *)(FPGA1_BASE | (0x151 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RLOADARM_A1_RX_00              (*((volatile short  *)(FPGA1_BASE | (0x152 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_RLOADARM_A1_RX_01              (*((volatile short  *)(FPGA1_BASE | (0x153 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_RLOADARM_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x154 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_RDANCER_A1
#define F1_MOTO_RDANCER_A1_TX_00               (*((volatile short  *)(FPGA1_BASE | (0x158 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RDANCER_A1_TX_01               (*((volatile short  *)(FPGA1_BASE | (0x159 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_RDANCER_A1_RX_00               (*((volatile short  *)(FPGA1_BASE | (0x15A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_RDANCER_A1_RX_01               (*((volatile short  *)(FPGA1_BASE | (0x15B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_RDANCER_A1_WORDS               (*((volatile short  *)(FPGA1_BASE | (0x15C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_LDANCER1_A1
#define F1_MOTO_LDANCER1_A1_TX_00              (*((volatile short  *)(FPGA1_BASE | (0x160 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LDANCER1_A1_TX_01              (*((volatile short  *)(FPGA1_BASE | (0x161 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LDANCER1_A1_RX_00              (*((volatile short  *)(FPGA1_BASE | (0x162 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_LDANCER1_A1_RX_01              (*((volatile short  *)(FPGA1_BASE | (0x163 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_LDANCER1_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x164 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_LDANCER2_A1
#define F1_MOTO_LDANCER2_A1_TX_00              (*((volatile short  *)(FPGA1_BASE | (0x168 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LDANCER2_A1_TX_01              (*((volatile short  *)(FPGA1_BASE | (0x169 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LDANCER2_A1_RX_00              (*((volatile short  *)(FPGA1_BASE | (0x16A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_LDANCER2_A1_RX_01              (*((volatile short  *)(FPGA1_BASE | (0x16B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_LDANCER2_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x16C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_DRYER_LID_A1
#define F1_MOTO_DRYER_LID_A1_TX_00             (*((volatile short  *)(FPGA1_BASE | (0x170 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DRYER_LID_A1_TX_01             (*((volatile short  *)(FPGA1_BASE | (0x171 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DRYER_LID_A1_RX_00             (*((volatile short  *)(FPGA1_BASE | (0x172 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_DRYER_LID_A1_RX_01             (*((volatile short  *)(FPGA1_BASE | (0x173 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_DRYER_LID_A1_WORDS             (*((volatile short  *)(FPGA1_BASE | (0x174 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_DH_LID_A1
#define F1_MOTO_DH_LID_A1_TX_00                (*((volatile short  *)(FPGA1_BASE | (0x178 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DH_LID_A1_TX_01                (*((volatile short  *)(FPGA1_BASE | (0x179 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_DH_LID_A1_RX_00                (*((volatile short  *)(FPGA1_BASE | (0x17A * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_DH_LID_A1_RX_01                (*((volatile short  *)(FPGA1_BASE | (0x17B * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_DH_LID_A1_WORDS                (*((volatile short  *)(FPGA1_BASE | (0x17C * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_LPIVOT1_A1
#define F1_MOTO_LPIVOT1_A1_TX_00               (*((volatile short  *)(FPGA1_BASE | (0x180 * Word1OrByte2))))    //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LPIVOT1_A1_TX_01               (*((volatile short  *)(FPGA1_BASE | (0x181 * Word1OrByte2))))    //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F1_MOTO_LPIVOT1_A1_RX_00               (*((volatile short  *)(FPGA1_BASE | (0x182 * Word1OrByte2))))    //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F1_MOTO_LPIVOT1_A1_RX_01               (*((volatile short  *)(FPGA1_BASE | (0x183 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_MOTO_LPIVOT1_A1_WORDS               (*((volatile short  *)(FPGA1_BASE | (0x184 * Word1OrByte2))))    //The amount of spi words (usually byte sized) per transmission.

//SSI
#define F1_LDANCER1_ROTENC_DATA_p_RX_msb       (*((volatile short  *)(FPGA1_BASE | (0x190 * Word1OrByte2))))    //16 bit MSB if nessesary
#define F1_LDANCER1_ROTENC_DATA_p_RX_lsb       (*((volatile short  *)(FPGA1_BASE | (0x191 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_LDANCER1_ROTENC_DATA_p_TX           (*((volatile short  *)(FPGA1_BASE | (0x197 * Word1OrByte2))))    //This register triggers a TX transmission

#define F1_LDANCER2_ROTENC_DATA_p_RX_msb       (*((volatile short  *)(FPGA1_BASE | (0x198 * Word1OrByte2))))    //16 bit MSB if nessesary
#define F1_LDANCER2_ROTENC_DATA_p_RX_lsb       (*((volatile short  *)(FPGA1_BASE | (0x199 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_LDANCER2_ROTENC_DATA_p_TX           (*((volatile short  *)(FPGA1_BASE | (0x19F * Word1OrByte2))))    //This register triggers a TX transmission

#define F1_LSPARE_ROTENC_DATA_p_RX_msb         (*((volatile short  *)(FPGA1_BASE | (0x1a0 * Word1OrByte2))))    //16 bit MSB if nessesary
#define F1_LSPARE_ROTENC_DATA_p_RX_lsb         (*((volatile short  *)(FPGA1_BASE | (0x1a1 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_LSPARE_ROTENC_DATA_p_TX             (*((volatile short  *)(FPGA1_BASE | (0x1A7 * Word1OrByte2))))    //This register triggers a TX transmission

#define F1_RDANCER_ROTENC_DATA_p_RX_msb        (*((volatile short  *)(FPGA1_BASE | (0x1a8 * Word1OrByte2))))    //16 bit MSB if nessesary
#define F1_RDANCER_ROTENC_DATA_p_RX_lsb        (*((volatile short  *)(FPGA1_BASE | (0x1a9 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_RDANCER_ROTENC_DATA_p_TX            (*((volatile short  *)(FPGA1_BASE | (0x1AF * Word1OrByte2))))    //This register triggers a TX transmission

#define F1_RSPARE_ROTENC_DATA_p_RX_msb         (*((volatile short  *)(FPGA1_BASE | (0x1b0 * Word1OrByte2))))    //16 bit MSB if nessesary
#define F1_RSPARE_ROTENC_DATA_p_RX_lsb         (*((volatile short  *)(FPGA1_BASE | (0x1b1 * Word1OrByte2))))    //The 16 Lsb bits of the shifted in data.
#define F1_RSPARE_ROTENC_DATA_p_TX             (*((volatile short  *)(FPGA1_BASE | (0x1B7 * Word1OrByte2))))    //This register triggers a TX transmission

#define F1_Tacho_reg0                          (*((volatile short  *)(FPGA1_BASE | (0x1E0 * Word1OrByte2))))    //This Register stores the Tacho counter
#define F1_Tacho_reg1                          (*((volatile short  *)(FPGA1_BASE | (0x1E1 * Word1OrByte2))))    //This Register stores the Tacho counter
#define F1_Tacho_reg2                          (*((volatile short  *)(FPGA1_BASE | (0x1E2 * Word1OrByte2))))    //This Register stores the Tacho counter
#define F1_Tacho_reg3                          (*((volatile short  *)(FPGA1_BASE | (0x1E3 * Word1OrByte2))))    //This Register stores the Tacho counter
#define F1_Tacho_reg4                          (*((volatile short  *)(FPGA1_BASE | (0x1E4 * Word1OrByte2))))    //This Register stores the Tacho counter
#define F1_Tacho_reg5                          (*((volatile short  *)(FPGA1_BASE | (0x1E5 * Word1OrByte2))))    //This Register stores the Tacho counter
#define F1_Tacho_reg6                          (*((volatile short  *)(FPGA1_BASE | (0x1E6 * Word1OrByte2))))    //This Register stores the Tacho counter
#define F1_Tacho_reg7                          (*((volatile short  *)(FPGA1_BASE | (0x1E7 * Word1OrByte2))))    //This Register stores the Tacho counter

//Prescaler
#define F1_Prescaler1_reg1                     (*((volatile short  *)(FPGA1_BASE | (0x1F0 * Word1OrByte2))))  //Parameter for prescaler divisions - 6bit ssi high duty cycle value for prescaler
#define F1_Prescaler1_reg2                     (*((volatile short  *)(FPGA1_BASE | (0x1F1 * Word1OrByte2))))  //Parameter for prescaler divisions - 6bit ssi low duty cycle value for prescaler
#define F1_Prescaler1_reg3                     (*((volatile short  *)(FPGA1_BASE | (0x1F2 * Word1OrByte2))))  //Parameter for prescaler divisions - 3bit spi moto low duty cycle value for pmw
#define F1_Prescaler1_reg4                     (*((volatile short  *)(FPGA1_BASE | (0x1F3 * Word1OrByte2))))  //Parameter for prescaler divisions - 3bit spi moto high duty cycle value for pmw
#define F1_Prescaler1_reg5                     (*((volatile short  *)(FPGA1_BASE | (0x1F4 * Word1OrByte2))))  //Parameter for prescaler divisions - amount of prescaled clocks for counter of signal All Tachos
#define F1_Prescaler1_reg6                     (*((volatile short  *)(FPGA1_BASE | (0x1F5 * Word1OrByte2))))  //Parameter for prescaler divisions
#define F1_Prescaler1_reg7                     (*((volatile short  *)(FPGA1_BASE | (0x1F6 * Word1OrByte2))))  //Parameter for prescaler divisions
#define F1_Prescaler1_reg8                     (*((volatile short  *)(FPGA1_BASE | (0x1F7 * Word1OrByte2))))  //Parameter for prescaler divisions

//Test
#define F1_Test                                (*((volatile short  *)(FPGA1_BASE | (0x1f8 * Word1OrByte2))))    //Readback not -gives the inverse of the written to value

// * * * * * * * * * * * * * * * * FPGA 2  * * * * * * * * * * * * * * * * //
//Version1
#define F2_Ver1_D                              (*((volatile short  *)(FPGA2_BASE | (0x00 * Word1OrByte2))))  //Version of Fpga is held here

//Version2
#define F2_Ver2_D                              (*((volatile short  *)(FPGA2_BASE | (0x08 * Word1OrByte2))))  //Version of Fpga is held here

//GPI shorterrupt LS_01 Registers
#define F2_GPI_LS1_D                           (*((volatile short  *)(FPGA2_BASE | (0x10 * Word1OrByte2))))    //Reads the direct values that are currently being sent to the fpga.
#define F2_GPI_LS1_L                           (*((volatile short  *)(FPGA2_BASE | (0x11 * Word1OrByte2))))    //Value of the latched shorterrupts that have occurred
#define F2_GPI_LS1_M                           (*((volatile short  *)(FPGA2_BASE | (0x12 * Word1OrByte2))))    //Value of the shorterrupt mask, Default is 0x0000

//GPI shorterrupt LS_02 Registers
#define F2_GPI_LS2_D                           (*((volatile short  *)(FPGA2_BASE | (0x18 * Word1OrByte2))))    //Reads the direct values that are currently being sent to the fpga.
#define F2_GPI_LS2_L                           (*((volatile short  *)(FPGA2_BASE | (0x19 * Word1OrByte2))))    //Value of the latched shorterrupts that have occurred
#define F2_GPI_LS2_M                           (*((volatile short  *)(FPGA2_BASE | (0x1a * Word1OrByte2))))    //Value of the shorterrupt mask, Default is 0x0000

//GPI shorterrupt LS_03 Registers
#define F2_GPI_LS3_D                           (*((volatile short  *)(FPGA2_BASE | (0x20 * Word1OrByte2))))     //Reads the direct values that are currently being sent to the fpga.
#define F2_GPI_LS3_L                           (*((volatile short  *)(FPGA2_BASE | (0x21 * Word1OrByte2))))     //Value of the latched shorterrupts that have occurred
#define F2_GPI_LS3_M                           (*((volatile short  *)(FPGA2_BASE | (0x22 * Word1OrByte2))))     //Value of the shorterrupt mask, Default is 0x0000

//Moto_Driver_NBUSY_register1
#define F2_Moto_Driver_NBUSY1_D                (*((volatile short  *)(FPGA2_BASE | (0x28 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F2_Moto_Driver_NBUSY1_L                (*((volatile short  *)(FPGA2_BASE | (0x29 * Word1OrByte2))))   //Value of the latched shorterrupts that have occurred
#define F2_Moto_Driver_NBUSY1_M                (*((volatile short  *)(FPGA2_BASE | (0x2a * Word1OrByte2))))   //Value of the shorterrupt mask, Default is 0x0000

//DISPENSER_VALVE_IN
#define F2_DISPENSER_VALVE_IN_Direct           (*((volatile short  *)(FPGA2_BASE | (0x030 * Word1OrByte2))))     //Reads the direct values that are currently being sent to the fpga.
#define F2_DISPENSER_VALVE_IN_Latched          (*((volatile short  *)(FPGA2_BASE | (0x031 * Word1OrByte2))))     //Value of the latched shorterrupts that have occurred
#define F2_DISPENSER_VALVE_IN_Mask             (*((volatile short  *)(FPGA2_BASE | (0x032 * Word1OrByte2))))     //Value of the shorterrupt mask, Default is 0x0000

//GPI_REGISTER1
#define F2_GPI_REGISTER1_Direct                (*((volatile short  *)(FPGA2_BASE | (0x038 * Word1OrByte2))))     //Reads the direct values that are currently being sent to the fpga.
#define F2_GPI_REGISTER1_Latched               (*((volatile short  *)(FPGA2_BASE | (0x039 * Word1OrByte2))))     //Value of the latched shorterrupts that have occurred
#define F2_GPI_REGISTER1_Mask                  (*((volatile short  *)(FPGA2_BASE | (0x03A * Word1OrByte2))))     //Value of the shorterrupt mask, Default is 0x0000

//LS_04
#define F2_LS_04_Direct                        (*((volatile short  *)(FPGA2_BASE | (0x040 * Word1OrByte2))))     //Version of Fpga is held here
#define F2_LS_04_Latched                       (*((volatile short  *)(FPGA2_BASE | (0x041 * Word1OrByte2))))     //Value of the latched shorterrupts that have occurred
#define F2_LS_04_Mask                          (*((volatile short  *)(FPGA2_BASE | (0x042 * Word1OrByte2))))     //Value of the shorterrupt mask, Default is 0x0000

//SPI_Busy_register1
#define F2_SPI_Busy1_Direct                    (*((volatile short  *)(FPGA2_BASE | (0x048 * Word1OrByte2))))     //Reads the direct values that are currently being sent to the fpga.
#define F2_SPI_Busy1_Latched                   (*((volatile short  *)(FPGA2_BASE | (0x049 * Word1OrByte2))))     //Value of the latched shorterrupts that have occurred
#define F2_SPI_Busy1_Mask                      (*((volatile short  *)(FPGA2_BASE | (0x04a * Word1OrByte2))))     //Value of the shorterrupt mask, Default is 0x0000

//SPI_Busy_register2
#define F2_SPI_Busy2_Direct                    (*((volatile short  *)(FPGA2_BASE | (0x050 * Word1OrByte2))))     //Reads the direct values that are currently being sent to the fpga.
#define F2_SPI_Busy2_Latched                   (*((volatile short  *)(FPGA2_BASE | (0x051 * Word1OrByte2))))     //Value of the latched shorterrupts that have occurred
#define F2_SPI_Busy2_Mask                      (*((volatile short  *)(FPGA2_BASE | (0x052 * Word1OrByte2))))     //Value of the shorterrupt mask, Default is 0x0000

//Moto_Driver_NSTBYRST_register1
#define F2_Moto_Driver_NSTBYRST1               (*((volatile short  *)(FPGA2_BASE | (0x059 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//DISPENSER_VALVE_OUT
#define F2_DISPENSER_VALVE_OUT                 (*((volatile short  *)(FPGA2_BASE | (0x061 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//Moto_Driver_SW_register1
#define F2_Moto_Driver_SW1                     (*((volatile short  *)(FPGA2_BASE | (0x069 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//CTRL
#define F2_CTRL                                (*((volatile short  *)(FPGA2_BASE | (0x071 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//GPO_REGISTER
#define F2_GPO_REGISTER                        (*((volatile short  *)(FPGA2_BASE | (0x079 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register
#define F2_Prescaler1_reg9                     (*((volatile short  *)(FPGA2_BASE | (0x081 * Word1OrByte2)))) //Parameter for prescaler divisions -amount of prescaled clocks for counter of signal Blower Tacho.
#define F2_Prescaler1_reg10                    (*((volatile short  *)(FPGA2_BASE | (0x089 * Word1OrByte2)))) //Parameter for prescaler divisions -amount of prescaled clocks clk input of pwm of signal F2_GPO_BLOWER_PWM. 8bits
#define F2_VALVE_VALUE                         (*((volatile short  *)(FPGA2_BASE | (0x091 * Word1OrByte2)))) //This register holds the vlave values for the vlave pulse counter

//SSI
#define F2_DISPENSER_ROTENC_DATA_p_1_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0C0 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_1_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0C1 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_DISPENSER_ROTENC_DATA_p_1_TX        (*((volatile short  *)(FPGA2_BASE | (0x0C7 * Word1OrByte2)))) //This register triggers a TX transmission

#define F2_DISPENSER_ROTENC_DATA_p_2_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0C8 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_2_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0C9 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_DISPENSER_ROTENC_DATA_p_2_TX        (*((volatile short  *)(FPGA2_BASE | (0x0Cf * Word1OrByte2)))) //This register triggers a TX transmission

#define F2_DISPENSER_ROTENC_DATA_p_3_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0D0 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_3_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0D1 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_3_TX        (*((volatile short  *)(FPGA2_BASE | (0x0D7 * Word1OrByte2)))) //This register triggers a TX transmission

#define F2_DISPENSER_ROTENC_DATA_p_4_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0D8 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_DISPENSER_ROTENC_DATA_p_4_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0D9 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_4_TX        (*((volatile short  *)(FPGA2_BASE | (0x0DF * Word1OrByte2)))) //This register triggers a TX transmission

#define F2_DISPENSER_ROTENC_DATA_p_5_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0E0 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_DISPENSER_ROTENC_DATA_p_5_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0E1 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_5_TX        (*((volatile short  *)(FPGA2_BASE | (0x0E7 * Word1OrByte2)))) //This register triggers a TX transmission

#define F2_DISPENSER_ROTENC_DATA_p_6_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0E8 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_6_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0E9 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_DISPENSER_ROTENC_DATA_p_6_TX        (*((volatile short  *)(FPGA2_BASE | (0x0EF * Word1OrByte2)))) //This register triggers a TX transmission

#define F2_DISPENSER_ROTENC_DATA_p_7_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0F0 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_7_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0F1 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_DISPENSER_ROTENC_DATA_p_7_TX        (*((volatile short  *)(FPGA2_BASE | (0x0F7 * Word1OrByte2)))) //This register triggers a TX transmission

#define F2_DISPENSER_ROTENC_DATA_p_8_RX_msb    (*((volatile short  *)(FPGA2_BASE | (0x0F8 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F2_DISPENSER_ROTENC_DATA_p_8_RX_lsb    (*((volatile short  *)(FPGA2_BASE | (0x0F9 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_DISPENSER_ROTENC_DATA_p_8_TX        (*((volatile short  *)(FPGA2_BASE | (0x0FF * Word1OrByte2)))) //This register triggers a TX transmission

//ANALOG_DYEINGH_TEMP1_1
#define F2_ANALOG_DYEINGH_TEMP1_1_TX_00        (*((volatile short  *)(FPGA2_BASE | (0x100 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP1_1_TX_01        (*((volatile short  *)(FPGA2_BASE | (0x101 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP1_1_RX_00        (*((volatile short  *)(FPGA2_BASE | (0x102 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DYEINGH_TEMP1_1_RX_01        (*((volatile short  *)(FPGA2_BASE | (0x103 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DYEINGH_TEMP1_1_WORDS        (*((volatile short  *)(FPGA1_BASE | (0x104 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//AN_ENCLOSURETEMP1_1
#define F2_AN_ENCLOSURETEMP1_1_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x108 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_AN_ENCLOSURETEMP1_1_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x109 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_AN_ENCLOSURETEMP1_1_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x10A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_AN_ENCLOSURETEMP1_1_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x10B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_AN_ENCLOSURETEMP1_1_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x10C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//ANALOG_DYEINGH_TEMP2
#define F2_ANALOG_DYEINGH_TEMP2_TX_00          (*((volatile short  *)(FPGA2_BASE | (0x110 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP2_TX_01          (*((volatile short  *)(FPGA2_BASE | (0x111 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP2_RX_00          (*((volatile short  *)(FPGA2_BASE | (0x112 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DYEINGH_TEMP2_RX_01          (*((volatile short  *)(FPGA2_BASE | (0x113 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DYEINGH_TEMP2_WORDS          (*((volatile short  *)(FPGA1_BASE | (0x104 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//AN_ENCLOSURETEMP2_1
#define F2_AN_ENCLOSURETEMP2_1_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x118 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_AN_ENCLOSURETEMP2_1_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x119 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_AN_ENCLOSURETEMP2_1_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x11A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_AN_ENCLOSURETEMP2_1_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x11B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_AN_ENCLOSURETEMP2_1_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x11C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//ANALOG_DYEINGH_TEMP3
#define F2_ANALOG_DYEINGH_TEMP3_1_TX_00        (*((volatile short  *)(FPGA2_BASE | (0x120 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP3_1_TX_01        (*((volatile short  *)(FPGA2_BASE | (0x121 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP3_1_RX_00        (*((volatile short  *)(FPGA2_BASE | (0x122 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DYEINGH_TEMP3_1_RX_01        (*((volatile short  *)(FPGA2_BASE | (0x123 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DYEINGH_TEMP3_1_WORDS        (*((volatile short  *)(FPGA1_BASE | (0x124 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//AN_ENCLOSURETEMP3_1
#define F2_AN_ENCLOSURETEMP3_1_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x128 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_AN_ENCLOSURETEMP3_1_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x129 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_AN_ENCLOSURETEMP3_1_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x12A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_AN_ENCLOSURETEMP3_1_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x12B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_AN_ENCLOSURETEMP3_1_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x12C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//ANALOG_DYEINGH_TEMP4
#define F2_ANALOG_DYEINGH_TEMP4_1_TX_00        (*((volatile short  *)(FPGA2_BASE | (0x130 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP4_1_TX_01        (*((volatile short  *)(FPGA2_BASE | (0x131 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP4_1_RX_00        (*((volatile short  *)(FPGA2_BASE | (0x132 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DYEINGH_TEMP4_1_RX_01        (*((volatile short  *)(FPGA2_BASE | (0x133 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DYEINGH_TEMP4_1_WORDS        (*((volatile short  *)(FPGA1_BASE | (0x134 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//ANALOG_DRYER_TEMP1
#define F2_ANALOG_DRYER_TEMP1_1_TX_00          (*((volatile short  *)(FPGA2_BASE | (0x138 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DRYER_TEMP1_1_TX_01          (*((volatile short  *)(FPGA2_BASE | (0x139 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DRYER_TEMP1_1_RX_00          (*((volatile short  *)(FPGA2_BASE | (0x13A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DRYER_TEMP1_1_RX_01          (*((volatile short  *)(FPGA2_BASE | (0x13B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DRYER_TEMP1_1_WORDS          (*((volatile short  *)(FPGA1_BASE | (0x13C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.


//ANALOG_DYEINGH_TEMP5
#define F2_ANALOG_DYEINGH_TEMP5_1_TX_00        (*((volatile short  *)(FPGA2_BASE | (0x140 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP5_1_TX_01        (*((volatile short  *)(FPGA2_BASE | (0x141 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DYEINGH_TEMP5_1_RX_00        (*((volatile short  *)(FPGA2_BASE | (0x142 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DYEINGH_TEMP5_1_RX_01        (*((volatile short  *)(FPGA2_BASE | (0x143 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DYEINGH_TEMP5_1_WORDS        (*((volatile short  *)(FPGA1_BASE | (0x144 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//ANALOG_DRYER_TEMP2
#define F2_ANALOG_DRYER_TEMP2_1_TX_00          (*((volatile short  *)(FPGA2_BASE | (0x148 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DRYER_TEMP2_1_TX_01          (*((volatile short  *)(FPGA2_BASE | (0x149 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DRYER_TEMP2_1_RX_00          (*((volatile short  *)(FPGA2_BASE | (0x14A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DRYER_TEMP2_1_RX_01          (*((volatile short  *)(FPGA2_BASE | (0x14B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DRYER_TEMP2_1_WORDS          (*((volatile short  *)(FPGA1_BASE | (0x14C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//ANALOG_MIXCHIP_TEMP
#define F2_ANALOG_MIXCHIP_TEMP_1_TX_00         (*((volatile short  *)(FPGA2_BASE | (0x150 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_MIXCHIP_TEMP_1_TX_01         (*((volatile short  *)(FPGA2_BASE | (0x151 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_MIXCHIP_TEMP_1_RX_00         (*((volatile short  *)(FPGA2_BASE | (0x152 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_MIXCHIP_TEMP_1_RX_01         (*((volatile short  *)(FPGA2_BASE | (0x153 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_MIXCHIP_TEMP_1_WORDS         (*((volatile short  *)(FPGA1_BASE | (0x154 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//ANALOG_DRYER_TEMP3
#define F2_ANALOG_DRYER_TEMP3_1_TX_00          (*((volatile short  *)(FPGA2_BASE | (0x158 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DRYER_TEMP3_1_TX_01          (*((volatile short  *)(FPGA2_BASE | (0x159 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_ANALOG_DRYER_TEMP3_1_RX_00          (*((volatile short  *)(FPGA2_BASE | (0x15A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_ANALOG_DRYER_TEMP3_1_RX_01          (*((volatile short  *)(FPGA2_BASE | (0x15B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_ANALOG_DRYER_TEMP3_1_WORDS          (*((volatile short  *)(FPGA1_BASE | (0x15C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1
#define F2_MOTO_DISPENSER_A1_1_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x190 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_1_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x191 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_1_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x192 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_1_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x193 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_1_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x194 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1_2
#define F2_MOTO_DISPENSER_A1_2_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x198 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_2_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x199 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_2_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x19A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_2_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x19B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_2_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x19C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1_3
#define F2_MOTO_DISPENSER_A1_3_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x1A0 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_3_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x1A1 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_3_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x1A2 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_3_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x1A3 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_3_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x1A4 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1_4
#define F2_MOTO_DISPENSER_A1_4_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x1A8 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_4_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x1A9 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_4_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x1AA * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_4_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x1AB * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_4_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x1AC * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1_5
#define F2_MOTO_DISPENSER_A1_5_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x1B0 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_5_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x1B1 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_5_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x1B2 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_5_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x1B3 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_5_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x1B4 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1_6
#define F2_MOTO_DISPENSER_A1_6_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x1B8 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_6_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x1B9 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_6_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x1BA * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_6_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x1BB * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_6_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x1BC * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1_7
#define F2_MOTO_DISPENSER_A1_7_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x1C0 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_7_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x1C1 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_7_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x1C2 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_7_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x1C3 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_7_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x1C4 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//MOTO_DISPENSER_A1_8
#define F2_MOTO_DISPENSER_A1_8_TX_00           (*((volatile short  *)(FPGA2_BASE | (0x1C8 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_8_TX_01           (*((volatile short  *)(FPGA2_BASE | (0x1C9 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F2_MOTO_DISPENSER_A1_8_RX_00           (*((volatile short  *)(FPGA2_BASE | (0x1CA * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F2_MOTO_DISPENSER_A1_8_RX_01           (*((volatile short  *)(FPGA2_BASE | (0x1CB * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F2_MOTO_DISPENSER_A1_8_WORDS           (*((volatile short  *)(FPGA1_BASE | (0x1CC * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

#define F2_Tacho_reg0                          (*((volatile short  *)(FPGA1_BASE | (0x1E0 * Word1OrByte2))))    //This Register stores the Tacho counter

//Prescaler
#define F2_Prescaler1_reg0                     (*((volatile short  *)(FPGA1_BASE | (0x1F0 * Word1OrByte2))))  //Parameter for prescaler divisions - 6bit ssi high duty cycle value for prescaler
#define F2_Prescaler1_reg1                     (*((volatile short  *)(FPGA1_BASE | (0x1F1 * Word1OrByte2))))  //Parameter for prescaler divisions - 6bit ssi low duty cycle value for prescaler
#define F2_Prescaler1_reg2                     (*((volatile short  *)(FPGA1_BASE | (0x1F2 * Word1OrByte2))))  //Parameter for prescaler divisions - 3bit spi temp low duty cycle value for pmw
#define F2_Prescaler1_reg3                     (*((volatile short  *)(FPGA1_BASE | (0x1F3 * Word1OrByte2))))  //Parameter for prescaler divisions - 3bit spi temp high duty cycle value for pmw
#define F2_Prescaler1_reg4                     (*((volatile short  *)(FPGA1_BASE | (0x1F4 * Word1OrByte2))))  //Parameter for prescaler divisions - 3bit spi moto low duty cycle value for pmw
#define F2_Prescaler1_reg5                     (*((volatile short  *)(FPGA1_BASE | (0x1F5 * Word1OrByte2))))  //Parameter for prescaler divisions - 3bit spi moto high duty cycle value for pmw
#define F2_Prescaler1_reg6                     (*((volatile short  *)(FPGA1_BASE | (0x1F6 * Word1OrByte2))))  //Parameter for prescaler divisions - 8bit BLOWER low duty cycle value for pmw
#define F2_Prescaler1_reg7                     (*((volatile short  *)(FPGA1_BASE | (0x1F7 * Word1OrByte2))))  //Parameter for prescaler divisions - 8bit BLOWER high duty cycle value for pmw

//Test
#define F2_Test                                (*((volatile short  *)(FPGA2_BASE | (0x1F8 * Word1OrByte2)))) //Readback not - gives the inverse of the written to value

// * * * * * * * * * * * * * * * * FPGA 3  * * * * * * * * * * * * * * * * //

//Version1
#define F3_Ver1_D                              (*((volatile short  *)(FPGA3_BASE | (0x0 * Word1OrByte2))))  //Version of Fpga is held here

//Version2
#define F3_Ver2_D                              (*((volatile short  *)(FPGA3_BASE | (0x8 * Word1OrByte2))))  //Version of Fpga is held here

//GPI 01
#define F3_GPI_01_D                            (*((volatile short  *)(FPGA3_BASE | (0x10 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_GPI_01_L                            (*((volatile short  *)(FPGA3_BASE | (0x11 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_GPI_01_M                            (*((volatile short  *)(FPGA3_BASE | (0x12 * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//MIDTANK 01
#define F3_MIDTANK_01_Direct                   (*((volatile short  *)(FPGA3_BASE | (0x018 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_MIDTANK_01_Latched                  (*((volatile short  *)(FPGA3_BASE | (0x019 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_MIDTANK_01_Mask                     (*((volatile short  *)(FPGA3_BASE | (0x01a * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//MIDTANK 02
#define F3_MIDTANK_02_Direct                   (*((volatile short  *)(FPGA3_BASE | (0x020 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_MIDTANK_02_Latched                  (*((volatile short  *)(FPGA3_BASE | (0x021 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_MIDTANK_02_Mask                     (*((volatile short  *)(FPGA3_BASE | (0x022 * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//DISPENSER_ROTENC_IN
#define F3_DISPENSER_ROTENC_IN_Direct          (*((volatile short  *)(FPGA3_BASE | (0x028 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_DISPENSER_ROTENC_IN_Latched         (*((volatile short  *)(FPGA3_BASE | (0x029 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_DISPENSER_ROTENC_IN_Mask            (*((volatile short  *)(FPGA3_BASE | (0x02A * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//Moto_Driver_NBUSY_register1
#define F3_Moto_Driver_NBUSY1_Direct           (*((volatile short  *)(FPGA3_BASE | (0x030 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_Moto_Driver_NBUSY1_Latched          (*((volatile short  *)(FPGA3_BASE | (0x031 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_Moto_Driver_NBUSY1_Mask             (*((volatile short  *)(FPGA3_BASE | (0x032 * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//CARTx_PRES
#define F3_CARTx_PRES_02_Direct                (*((volatile short  *)(FPGA3_BASE | (0x038 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_CARTx_PRES_02_Latched               (*((volatile short  *)(FPGA3_BASE | (0x039 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_CARTx_PRES_02_Mask                  (*((volatile short  *)(FPGA3_BASE | (0x03A * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//LS_01
#define F3_LS_01_Direct                        (*((volatile short  *)(FPGA3_BASE | (0x040 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_LS_01_Latched                       (*((volatile short  *)(FPGA3_BASE | (0x041 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_LS_01_Mask                          (*((volatile short  *)(FPGA3_BASE | (0x042 * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//Spi_Busy_01
#define F3_busy_01_Direct                      (*((volatile short  *)(FPGA3_BASE | (0x050 * Word1OrByte2)))) //Reads the direct values that are currently being sent to the fpga.
#define F3_busy_01_Latched                     (*((volatile short  *)(FPGA3_BASE | (0x051 * Word1OrByte2)))) //Value of the latched shorterrupts that have occurred
#define F3_busy_01_Mask                        (*((volatile short  *)(FPGA3_BASE | (0x052 * Word1OrByte2)))) //Value of the shorterrupt mask, Default is 0x0000

//Moto_Driver_NSTBYRST_register1
#define F3_Moto_Driver_NSTBYRST1               (*((volatile short  *)(FPGA3_BASE | (0x059 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//GPO_01
#define F3_GPO_01_bus                          (*((volatile short  *)(FPGA3_BASE | (0x061 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//Moto_Driver_SW_register1
#define F3_Moto_Driver_SW1                     (*((volatile short  *)(FPGA3_BASE | (0x069 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//VALVE_OUT
#define F3_VALVE_OUT                           (*((volatile short  *)(FPGA3_BASE | (0x071 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//DISPENSER_ROTENC_OUT
#define F3_DISPENSER_ROTENC_OUT                (*((volatile short  *)(FPGA3_BASE | (0x079 * Word1OrByte2)))) //Writes to values. Readback thevaluessthat are currently in the GPO register

//QEI_SCREW_ROTENC
#define F3_SPARE1_ROTENC_lsb                   (*((volatile short  *)(FPGA3_BASE | (0x080 * Word1OrByte2)))) //Value of the lsb of the QEI register
#define F3_SPARE1_ROTENC_msb                   (*((volatile short  *)(FPGA3_BASE | (0x081 * Word1OrByte2)))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F3_SPARE1_ROTENC_index                 (*((volatile short  *)(FPGA3_BASE | (0x082 * Word1OrByte2)))) //value of index counter

//QEI_RSPARE_ROTENC
#define F3_RSPARE_ROTENC_lsb                   (*((volatile short  *)(FPGA3_BASE | (0x088 * Word1OrByte2)))) //Value of the lsb of the QEI register
#define F3_RSPARE_ROTENC_msb                   (*((volatile short  *)(FPGA3_BASE | (0x089 * Word1OrByte2)))) //10bits Value of the Msb of the QEI register, 1bit Direction of movement, 5bits Reserved
#define F3_RSPARE_ROTENC_index                 (*((volatile short  *)(FPGA3_BASE | (0x08a * Word1OrByte2)))) //value of index counter

//SPI_MOTO_RLOADING_A1
#define F3_MOTO_SPARE1_1_A1_TX_00              (*((volatile short  *)(FPGA3_BASE | (0x100 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE1_1_A1_TX_01              (*((volatile short  *)(FPGA3_BASE | (0x101 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE1_1_A1_RX_00              (*((volatile short  *)(FPGA3_BASE | (0x102 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F3_MOTO_SPARE1_1_A1_RX_01              (*((volatile short  *)(FPGA3_BASE | (0x103 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F3_MOTO_SPARE1_1_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x104 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//SPI_MOTO_RDRIVING_A1
#define F3_MOTO_SPARE1_2_A1_TX_00              (*((volatile short  *)(FPGA3_BASE | (0x108 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE1_2_A1_TX_01              (*((volatile short  *)(FPGA3_BASE | (0x109 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE1_2_A1_RX_00              (*((volatile short  *)(FPGA3_BASE | (0x10A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F3_MOTO_SPARE1_2_A1_RX_01              (*((volatile short  *)(FPGA3_BASE | (0x10B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F3_MOTO_SPARE1_2_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x10C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_LDRIVING_A1
#define F3_MOTO_SPARE2_1_A1_TX_00              (*((volatile short  *)(FPGA3_BASE | (0x110 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE2_1_A1_TX_01              (*((volatile short  *)(FPGA3_BASE | (0x111 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE2_1_A1_RX_00              (*((volatile short  *)(FPGA3_BASE | (0x112 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F3_MOTO_SPARE2_1_A1_RX_01              (*((volatile short  *)(FPGA3_BASE | (0x113 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F3_MOTO_SPARE2_1_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x114 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//SPI_F1_MOTO_LLOADING_A1
#define F3_MOTO_SPARE2_2_A1_TX_00              (*((volatile short  *)(FPGA3_BASE | (0x118 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE2_2_A1_TX_01              (*((volatile short  *)(FPGA3_BASE | (0x119 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE2_2_A1_RX_00              (*((volatile short  *)(FPGA3_BASE | (0x11A * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F3_MOTO_SPARE2_2_A1_RX_01              (*((volatile short  *)(FPGA3_BASE | (0x11B * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F3_MOTO_SPARE2_2_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x11C * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

#define F3_MOTO_SPARE3_1_A1_TX_00              (*((volatile short  *)(FPGA3_BASE | (0x120 * Word1OrByte2)))) //The second register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE3_1_A1_TX_01              (*((volatile short  *)(FPGA3_BASE | (0x120 * Word1OrByte2)))) //The first register to be shifted out of the spi. The msb bit of this register is shifted out first.
#define F3_MOTO_SPARE3_1_A1_RX_00              (*((volatile short  *)(FPGA3_BASE | (0x122 * Word1OrByte2)))) //The 8 msb bits of the shifted in bits. The 8 msb bits of this register are zeros.
#define F3_MOTO_SPARE3_1_A1_RX_01              (*((volatile short  *)(FPGA3_BASE | (0x123 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F3_MOTO_SPARE3_1_A1_WORDS              (*((volatile short  *)(FPGA1_BASE | (0x124 * Word1OrByte2)))) //The amount of spi words (usually byte sized) per transmission.

//SSI
#define F3_SPARE1_ROTENC_DATA_p_1_RX_msb       (*((volatile short  *)(FPGA3_BASE | (0x160 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F3_SPARE1_ROTENC_DATA_p_1_RX_lsb       (*((volatile short  *)(FPGA3_BASE | (0x161 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F3_SPARE1_ROTENC_DATA_p_1_TX           (*((volatile short  *)(FPGA3_BASE | (0x167 * Word1OrByte2)))) //This register triggers a TX transmission

#define F3_SPARE2_ROTENC_DATA_p_2_RX_msb       (*((volatile short  *)(FPGA3_BASE | (0x168 * Word1OrByte2)))) //16 bit MSB if nessesary
#define F3_SPARE2_ROTENC_DATA_p_2_RX_lsb       (*((volatile short  *)(FPGA3_BASE | (0x169 * Word1OrByte2)))) //The 16 Lsb bits of the shifted in data.
#define F3_SPARE2_ROTENC_DATA_p_1_TX           (*((volatile short  *)(FPGA3_BASE | (0x16F * Word1OrByte2)))) //This register triggers a TX transmission

#define F3_SW_RESET_reg                        (*((volatile short  *)(FPGA3_BASE | (0x1E8 * Word1OrByte2)))) //This register resets the MCU

//Prescaler
#define F3_Prescaler1_reg1                     (*((volatile short  *)(FPGA3_BASE | (0x1F0 * Word1OrByte2)))) //Parameter for prescaler divisions - 6bit ssi high duty cycle value for prescale
#define F3_Prescaler1_reg2                     (*((volatile short  *)(FPGA3_BASE | (0x1F1 * Word1OrByte2)))) //Parameter for prescaler divisions - 6bit ssi low duty cycle value for prescaler
#define F3_Prescaler1_reg3                     (*((volatile short  *)(FPGA3_BASE | (0x1F2 * Word1OrByte2)))) //Parameter for prescaler divisions - 3bit spi moto low duty cycle value for pmw
#define F3_Prescaler1_reg4                     (*((volatile short  *)(FPGA3_BASE | (0x1F3 * Word1OrByte2)))) //Parameter for prescaler divisions - 3bit spi moto high duty cycle value for pmw

#define F3_Prescaler1_reg5                     (*((volatile short  *)(FPGA3_BASE | (0x1F4 * Word1OrByte2)))) //Parameter for prescaler divisions
#define F3_Prescaler1_reg6                     (*((volatile short  *)(FPGA3_BASE | (0x1F5 * Word1OrByte2)))) //Parameter for prescaler divisions
#define F3_Prescaler1_reg7                     (*((volatile short  *)(FPGA3_BASE | (0x1F6 * Word1OrByte2)))) //Parameter for prescaler divisions
#define F3_Prescaler1_reg8                     (*((volatile short  *)(FPGA3_BASE | (0x1F7 * Word1OrByte2)))) //Parameter for prescaler divisions
//Test
#define F3_Test                                (*((volatile short  *)(FPGA3_BASE | (0x1F8 * Word1OrByte2)))) //Readback not - gives the inverse of the written to value

//1 Version1_Direct
typedef union
{
    struct
    {
        unsigned char Month; //0-7
        unsigned char Day;  //8-15
    }bytes;
    unsigned short ushort;
}VER1;

//4 Version2_Direct
typedef union
{
    struct
    {
        unsigned char Ver_num; //0-7
        unsigned char Year;  //8-15
    }bytes;
    unsigned short ushort;
}VER2;

//16 Moto_Driver_NBUSY_register1
typedef union
{
    struct
    {
        bool F1_MOTO_LPIVOT1_A1_NBUSY       : 1; //0
        bool F1_MOTO_LLOADING_A1_NBUSY      : 1; //1
        bool F1_MOTO_LDRIVING_A1_NBUSY      : 1; //2
        bool F1_MOTO_LDANCER2_A1_NBUSY      : 1; //3
        bool F1_MOTO_LDANCER1_A1_NBUSY      : 1; //4
        bool F1_MOTO_DRYER_LOADARM_A1_NBUSY : 1; //5
        bool F1_MOTO_DRYER_LID_A1_NBUSY : 1; //6
        bool F1_MOTO_DRYER_DRIVING_A1_NBUSY : 1; //7
        bool F1_MOTO_DH_LID_A1_NBUSY : 1; //8
        bool F1_MOTO_DH_CLEANMECH_A1_NBUSY : 1; //9
        bool F1_MOTO_DH_CLEANHEAD_A1_NBUSY : 1; //10
        unsigned char RESERVE:5; //11-15
    }bits;
    unsigned short ushort;
}Mot_NBUSY1;

//19 Moto_Driver_NBUSY_register2
typedef union
{
    struct
    {
        bool F1_MOTO_WINDER_A1_NBUSY    : 1; //0
        bool F1_MOTO_SCREW_A1_NBUSY     : 1; //1
        bool F1_MOTO_RLOADING_A1_NBUSY  : 1; //2
        bool F1_MOTO_RLOADARM_A1_NBUSY  : 1; //3
        bool F1_MOTO_RDRIVING_A1_NBUSY  : 1; //4
        bool F1_MOTO_RDANCER_A1_NBUSY   : 1; //5
        unsigned char RESERVE1          : 2; // 6-7
        unsigned char RESERVE2;              // 8-15
    }bits;
    unsigned short ushort;
}Mot_NBUSY2;


//29 + 32 SPI_Busy_register1 + SPI_Busy_register2
typedef union
{
    struct
    {
        unsigned char SPI_Busy_1_D;
        unsigned char SPI_Busy_2_D;
    }ushort;
    unsigned int uint;
}SPI_BUSY;

//35 Moto_Driver_NSTBYRST1
typedef union
{
    struct
    {
        bool LPIVOT1 : 1;  //0
        bool LLOADING : 1; //1
        bool LDRIVING : 1; //2
        bool LDANCER2 : 1; //3
        bool LDANCER1 : 1; //4
        bool DRYER_LOADARM : 1; //5
        bool DRYER_LID : 1; //6
        bool DRYER_DRIVING : 1; //7
        bool DH_LID : 1; //8
        bool DH_CLEANMECH : 1; //9
        bool DH_CLEANHEAD : 1; //10
        unsigned char RESERVE:5; //11-15
    }bits;
    unsigned short ushort;
}MOT_NSTBYRST1;



//36 Moto_Driver_NSTBYRST2
typedef union
{
    struct
    {
        bool WINDER : 1;  //0
        bool SCREW : 1; //1
        bool RLOADING : 1; //2
        bool RLOADARM : 1; //3
        bool RDRIVING : 1; //4
        bool RDANCER : 1; //5
        unsigned char RESERVE1:2; // 6-7
        unsigned char RESERVE2; // 8-15
    }bits;
    unsigned short ushort;
}MOT_NSTBYRST2;

//37 Moto_Driver_SW_register1 - Moto_Driver_SW1
typedef union
{
    struct
    {
        bool LPIVOT1 : 1; //0
        bool LLOADING : 1; //1
        bool LDRIVING : 1; //2
        bool LDANCER2 : 1; //3
        bool LDANCER1 : 1; //4
        bool DRYER_LOADARM : 1; //5
        bool DRYER_LID : 1; //6
        bool DRYER_DRIVING; //7
        bool DH_LID : 1; //8
        bool DH_CLEANMECH : 1; //9
        bool DH_CLEANHEAD : 1; //10
        bool GPO_TFEED_BREAK_1 : 1; //11
        bool GPO_TFEED_BREAK_2 : 1; //12
        unsigned char RESERVE:3; // 13-15
    }bits;
    unsigned short ushort;
}MOT_SW1;

//38 Moto_Driver_SW_register2 - Moto_Driver_SW2
typedef union
{
    struct
    {
    bool F1_MOTO_WINDER_A1_SW : 1; //0
    bool F1_MOTO_SCREW_A1_SW : 1; //1
    bool F1_MOTO_RLOADING_A1_SW : 1; //2
    bool F1_MOTO_RLOADARM_A1_SW : 1; //3
    bool F1_MOTO_RDRIVING_A1_SW : 1; //4
    bool F1_MOTO_RDANCER_A1_SW : 1; //5
    unsigned char RESERVE1:2; // 6-7
    unsigned char RESERVE2; // 8-15
    }bits;
    unsigned short ushort;
}MOT_SW2;



//308 GPO_01
typedef union
{
    struct
    {
        bool F3_GPO_LED4 : 1; //0
        bool F3_GPO_LED3 : 1; //1
        bool F3_GPO_LED2 : 1; //2
        bool F3_GPO_LED1 : 1; //3
        bool F3_GPO_EXTWINDER_SSR11_CTRL : 1; //4
        bool F3_GPO_BUZZER : 1; //4
        bool F3_SPARE2_ROTENC_CLK : 1; //6
        bool F3_SPARE1_ROTENC_CLK : 1; //7
        unsigned char RESERVE; // 8-15
    }bits;
    unsigned short ushort;
}GP_Out_01;



//------------------------------ MOTOR DRIVER L_6470 ------------------------------

typedef union
{
    struct
    {
        unsigned short LSB;
        unsigned short MSB;
    }ushort;
    unsigned int uint;
}INT2SHORT;//16->32

//enum
//{
//    RLOADING,
//    RDRIVING,
//    F1_LDRIVING,
//    F1_LLOADING,
//    F1_DRYER_LOADARM,
//    F1_DRYER_DRIVING,
//    F1_DH_CLEANHEAD,
//    F1_DH_CLEANMECH,
//    F1_SCREW,
//    F1_WINDER,
//    RLOADARM,
//    RDANCER,
//    LDANCER1,
//    LDANCER2,
//    DRYER_LID,
//    DH_LID,
//    LPIVOT1,
//}SPI_TYPE;

////SPI
//typedef struct //S_SPI
//{
//    unsigned char Type;
//    unsigned int TX_MOSI; //32bit (Master Output Slave Input )
//    unsigned int RX_MISO; //24bit (Master Input  Slave Output)
//    //unsigned int BUSY;    //32bit
//
//}SPI;//SPI

/*
#define L6470_MOSI        (*((volatile short  *)(BASE | 0x0100)))
#define L6470_MISO        (*((volatile short  *)(BASE | 0x0200)))
#define L6470_CS          (*((volatile short  *)(BASE | 0x0300)))
#define L6470_CLK         (*((volatile short  *)(BASE | 0x0400)))
#define L6470_BUSY        (*((volatile short  *)(BASE | 0x0500)))
#define L6470_RESET       (*((volatile short  *)(BASE | 0x0600)))
#define L6470_TX          (*((volatile char *)(BASE | 0x0700)))
#define L6470_RX          (*((volatile char *)(BASE | 0x0800)))
*/

//L6470_MOSI = 0x00;