Software/Visual_Studio/Tango.UnitTesting/Helper.cs


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
generated by cgit v1.3.1 (git 2.54.0) at 2026-07-26 22:58:34 +0000
 

er.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 | F3_VALVE_OUT, MIDTANK2MANIF1_VALVE_2); 
                break;
             case 6:
                	stubManager.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 | F3_VALVE_OUT, CART2MIDTANK2_VALVE_2); 
					stubManager.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 | F3_VALVE_OUT, MIDTANK2MANIF2_VALVE_2); 
                break;
             case 7:
                	stubManager.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 | F3_VALVE_OUT, CART2MIDTANK3_VALVE_2); 
					stubManager.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 | F3_VALVE_OUT, MIDTANK2MANIF3_VALVE_2); 
                break;
             case 8:
                	stubManager.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 | F3_VALVE_OUT, CART2MIDTANK4_VALVE_2); 
					stubManager.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 | F3_VALVE_OUT, MIDTANK2MANIF4_VALVE_2); 
                break;
			 default:
					stubManager.Run<StubFpgaWriteRegResponse>("StubFpgaWriteRegRequest" ,FPGA3 + F3_VALVE_OUT, 0); // OFF
			 	break;
    }	
	
	if(MidTank_No > 0 && MidTank_No < 9)
	{
			stubManager.Write("Open Valves #"); 
			stubManager.Write(MidTank_No);
			stubManager.Write("\n");
	}
	else
	{
			stubManager.WriteLine("Close all Valves !"); 
	}
}