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/*
* PowerSTEP01.h
* //Based on:
* //https://os.mbed.com/teams/ST/code/X_NUCLEO_IHM03A1/file/2fbfe0cd8d4d/Components/powerstep01/powerstep01.h/
*
* Created on: Mar 5, 2019
* Author: avi
*/
#ifndef DRIVERS_FPGA_MOTORS_DRIVER_POWERSTEP01_H_
#define DRIVERS_FPGA_MOTORS_DRIVER_POWERSTEP01_H_
//powerSTEP01
#define x_POWERSTEP01_GATECFG1 0x18 //Gate driver configuration 11 bit
#define x_POWERSTEP01_GATECFG2 0x19 //Gate driver configuration 8 bit
#define x_POWERSTEP01_STATUS 0x1B //x_GET_STATUS is the same as in L6470
#define x_POWERSTEP01_CONFIG 0x1A
#define x_KVAL_TVAL_HOLD 0x09
#define x_KVAL_TVAL_RUN 0x0A
#define x_KVAL_TVAL_ACC 0x0B
#define x_KVAL_TVAL_DEC 0x0C
#define x_ST_SLP_T_FAST 0x0E
#define x_FN_SLP_ACC_TON_MIN 0x0F
#define x_FN_SLP_DEC_TOFF_MIN 0x10
///Shift of TCC field in GATECFG1 register
#define POWERSTEP01_TCC_SHIFT (0)
///Shift of IGATE field in GATECFG1 register
#define POWERSTEP01_IGATE_SHIFT (5)
///Shift of TBOOST field in GATECFG1 register
#define POWERSTEP01_TBOOST_SHIFT (8)
///Shift of TBLANK field in GATECFG2 register
#define POWERSTEP01_TBLANK_SHIFT (5)
///Shift of TDT field in GATECFG2 register
#define POWERSTEP01_TDT_SHIFT (0)
/// masks for GATECFG1 register of PowerStep01
typedef enum {
POWERSTEP01_GATECFG1_TCC_MASK = ((uint16_t)0x001F),
POWERSTEP01_GATECFG1_IGATE_MASK = ((uint16_t)0x00E0),
POWERSTEP01_GATECFG1_TBOOST_MASK = ((uint16_t)0x0700),
POWERSTEP01_GATECFG1_WD_EN = ((uint16_t)0x0800)
} powerstep01_GateCfg1Masks_t;
/// Control current Time (field TCC of GATECFG1 register of PowerStep01)
typedef enum {
POWERSTEP01_TCC_125ns = (((uint8_t)0x00)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_250ns = (((uint8_t)0x01)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_375ns = (((uint8_t)0x02)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_500ns = (((uint8_t)0x03)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_625ns = (((uint8_t)0x04)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_750ns = (((uint8_t)0x05)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_875ns = (((uint8_t)0x06)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1125ns = (((uint8_t)0x08)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1250ns = (((uint8_t)0x09)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1375ns = (((uint8_t)0x0A)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1500ns = (((uint8_t)0x0B)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1625ns = (((uint8_t)0x0C)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1750ns = (((uint8_t)0x0D)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_1875ns = (((uint8_t)0x0E)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2000ns = (((uint8_t)0x0F)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2125ns = (((uint8_t)0x10)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2250ns = (((uint8_t)0x11)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2375ns = (((uint8_t)0x12)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2500ns = (((uint8_t)0x13)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2625ns = (((uint8_t)0x14)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2750ns = (((uint8_t)0x15)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_2875ns = (((uint8_t)0x16)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3000ns = (((uint8_t)0x17)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3125ns = (((uint8_t)0x18)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3250ns = (((uint8_t)0x19)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3375ns = (((uint8_t)0x1A)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3500ns = (((uint8_t)0x1B)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3625ns = (((uint8_t)0x1C)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3750ns = (((uint8_t)0x1D)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3750ns_bis = (((uint8_t)0x1E)<<POWERSTEP01_TCC_SHIFT),
POWERSTEP01_TCC_3750ns_ter = (((uint8_t)0x1F)<<POWERSTEP01_TCC_SHIFT)
} powerstep01_Tcc_t;
/// Igate options (GATECFG1 register of PowerStep01)
typedef enum {
POWERSTEP01_IGATE_4mA = (((uint8_t)0x00)<<POWERSTEP01_IGATE_SHIFT),
POWERSTEP01_IGATE_4mA_Bis = (((uint8_t)0x01)<<POWERSTEP01_IGATE_SHIFT),
POWERSTEP01_IGATE_8mA = (((uint8_t)0x02)<<POWERSTEP01_IGATE_SHIFT),
POWERSTEP01_IGATE_16mA = (((uint8_t)0x03)<<POWERSTEP01_IGATE_SHIFT),
POWERSTEP01_IGATE_24mA = (((uint8_t)0x04)<<POWERSTEP01_IGATE_SHIFT),
POWERSTEP01_IGATE_32mA = (((uint8_t)0x05)<<POWERSTEP01_IGATE_SHIFT),
POWERSTEP01_IGATE_64mA = (((uint8_t)0x06)<<POWERSTEP01_IGATE_SHIFT),
POWERSTEP01_IGATE_96mA = (((uint8_t)0x07)<<POWERSTEP01_IGATE_SHIFT),
} powerstep01_Igate_t;
/// Turn off boost time (TBOOST field of GATECFG1 register of PowerStep01)
typedef enum {
POWERSTEP01_TBOOST_0ns = (((uint8_t)0x00)<<POWERSTEP01_TBOOST_SHIFT),
POWERSTEP01_TBOOST_62_5__83_3__125ns = (((uint8_t)0x01)<<POWERSTEP01_TBOOST_SHIFT),
POWERSTEP01_TBOOST_125ns = (((uint8_t)0x02)<<POWERSTEP01_TBOOST_SHIFT),
POWERSTEP01_TBOOST_250ns = (((uint8_t)0x03)<<POWERSTEP01_TBOOST_SHIFT),
POWERSTEP01_TBOOST_375ns = (((uint8_t)0x04)<<POWERSTEP01_TBOOST_SHIFT),
POWERSTEP01_TBOOST_500ns = (((uint8_t)0x05)<<POWERSTEP01_TBOOST_SHIFT),
POWERSTEP01_TBOOST_750ns = (((uint8_t)0x06)<<POWERSTEP01_TBOOST_SHIFT),
POWERSTEP01_TBOOST_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TBOOST_SHIFT),
} powerstep01_Tboost_t;
/// External clock watchdog (WD_EN field of GATECFG1 register of PowerStep01)
typedef enum {
POWERSTEP01_WD_EN_DISABLE = ((uint16_t)0x0000),
POWERSTEP01_WD_EN_ENABLE = ((uint16_t) ((0x1) << 11))
} powerstep01_WdEn_t;
/// masks for GATECFG2 register of PowerStep01
typedef enum {
POWERSTEP01_GATECFG2_TDT = ((uint8_t)0x1F),
POWERSTEP01_GATECFG2_TBLANK = ((uint8_t)0xE0)
} powerstep01_GateCfg2Masks_t;
/// Blanking time (TBLANK field of GATECFG2 register of PowerStep01)
typedef enum {
POWERSTEP01_TBLANK_125ns = (((uint8_t)0x00)<<POWERSTEP01_TBLANK_SHIFT),
POWERSTEP01_TBLANK_250ns = (((uint8_t)0x01)<<POWERSTEP01_TBLANK_SHIFT),
POWERSTEP01_TBLANK_375ns = (((uint8_t)0x02)<<POWERSTEP01_TBLANK_SHIFT),
POWERSTEP01_TBLANK_500ns = (((uint8_t)0x03)<<POWERSTEP01_TBLANK_SHIFT),
POWERSTEP01_TBLANK_625ns = (((uint8_t)0x04)<<POWERSTEP01_TBLANK_SHIFT),
POWERSTEP01_TBLANK_750ns = (((uint8_t)0x05)<<POWERSTEP01_TBLANK_SHIFT),
POWERSTEP01_TBLANK_875ns = (((uint8_t)0x06)<<POWERSTEP01_TBLANK_SHIFT),
POWERSTEP01_TBLANK_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TBLANK_SHIFT),
} powerstep01_TBlank_t;
/// Dead time (TDT field of GATECFG2 register of PowerStep01)
typedef enum {
POWERSTEP01_TDT_125ns = (((uint8_t)0x00)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_250ns = (((uint8_t)0x01)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_375ns = (((uint8_t)0x02)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_500ns = (((uint8_t)0x03)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_625ns = (((uint8_t)0x04)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_750ns = (((uint8_t)0x05)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_875ns = (((uint8_t)0x06)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1125ns = (((uint8_t)0x08)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1250ns = (((uint8_t)0x09)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1375ns = (((uint8_t)0x0A)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1500ns = (((uint8_t)0x0B)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1625ns = (((uint8_t)0x0C)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1750ns = (((uint8_t)0x0D)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_1875ns = (((uint8_t)0x0E)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2000ns = (((uint8_t)0x0F)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2125ns = (((uint8_t)0x10)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2250ns = (((uint8_t)0x11)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2375ns = (((uint8_t)0x12)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2500ns = (((uint8_t)0x13)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2625ns = (((uint8_t)0x14)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2750ns = (((uint8_t)0x15)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_2875ns = (((uint8_t)0x16)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3000ns = (((uint8_t)0x17)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3125ns = (((uint8_t)0x18)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3250ns = (((uint8_t)0x19)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3375ns = (((uint8_t)0x1A)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3500ns = (((uint8_t)0x1B)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3625ns = (((uint8_t)0x1C)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3750ns = (((uint8_t)0x1D)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_3875ns = (((uint8_t)0x1E)<<POWERSTEP01_TDT_SHIFT),
POWERSTEP01_TDT_4000ns = (((uint8_t)0x1F)<<POWERSTEP01_TDT_SHIFT)
} powerstep01_Tdt_t;
#endif /* DRIVERS_FPGA_MOTORS_DRIVER_POWERSTEP01_H_ */
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